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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Appendix > Appendix A - Topics - Core > A.1 – Core Types Reference |
Canonical type definitions from coreLib/types_core.h. All emulator subsystems use these types for architectural values.
Type |
Data Type |
Description |
|---|---|---|
ASNType |
quint16 |
Address Space Number (EV6 uses 8-bit ASNs; stored wider for safety) |
VAType |
quint64 |
Canonical virtual address (sign-extended, PAL/TLB safe) |
PAType |
quint64 |
Physical address (up to 44-bit EV6, stored in 64-bit container) |
VPNType |
quint64 |
Virtual Page Number (VA >> PAGE_SHIFT) |
PFNType |
quint64 |
Page Frame Number (EV6 PFN bits 52:32) |
TAGType |
quint64 |
Canonical TLB tag key (VPN + ASN + realm + sizeClass) |
PTEType |
quint64 |
Page Table Entry raw value |
FPCRType |
quint64 |
Floating Point Control Register value |
CMType |
quint8 |
Current Mode (0=Kernel, 1=Executive, 2=Supervisor, 3=User) |
CPUIdType |
quint8 |
CPU identifier (0..MAX_CPUS-1) |
SC_Type |
quint8 |
Size class / granularity hint (TLB superpage encoding) |
PermMask |
quint8 |
Compressed TLB permission mask (read/write enables) |
Realm |
enum |
Translation realm selector (I = Instruction, D = Data) |
ReplacementPolicy |
enum |
Cache/TLB replacement policy (SRRIP, Clock, Random) |
Architectural Constants:
Constant |
Value |
Description |
|---|---|---|
PAGE_SHIFT |
13 |
EV6 base page shift (8 KB pages) |
PAGE_SIZE |
8192 |
EV6 base page size (bytes) |
ASN_MAX |
256 |
Maximum ASN count (8-bit) |
CPU_ID_INVALID |
0xFF |
Invalid CPU sentinel |
MAX_CPUS |
qint32 |
System-wide CPU limit |
PFN_WIDTH |
int |
PFN width (architectural, EV6) |
PFN_SHIFT |
unsigned |
PFN bit shift in PTE (EV6 default) |
See Also: coreLib/types_core.h; Chapter 17 – Address Translation, TLB, and PTE.