ASA-EMulatR Reference Guide > Introduction > Appendix > Appendix A - Topics - Core > A.2 – EV6 Internal Processor Register (IPR) Reference

This appendix lists all EV6 Internal Processor Registers (IPRs) as implemented in ASA-EmulatR. IPRs are accessed exclusively through HW_MFPR (opcode 0x19, read) and HW_MTPR (opcode 0x1D, write), both of which are legal only in PAL mode. Access outside PAL mode faults with OPCDEC.

IBox IPRs (I):

Index	Mnemonic	Access	Description
0	ITB_TAG	WO	ITB tag write (VA for TLB fill)
1	ITB_PTE	WO	ITB PTE write (page table entry for TLB fill)
2	ITB_IAP	WO	ITB invalidate all process (non-ASM entries)
3	ITB_IA	WO	ITB invalidate all
4	ITB_IS	WO	ITB invalidate single (by VA)
6	EXC_ADDR	RO	Exception address (faulting/return PC)
7	IVA_FORM	RO	I-stream VA format (formatted faulting VA)
8–9	IER_CM	RW	Interrupt enable / current mode (K=0, E=1, S=2, U=3)
10	IER	RW	Interrupt enable register
12	SIRR	RW	Software interrupt request register (bits [15:1] for IPL 1–15)
13	ISUM	RO	Interrupt summary register
14	HW_INT_CLR	WO	Hardware interrupt clear
15	EXC_SUM	RO	Exception summary (arithmetic exception details)
16	PAL_BASE	RW	PAL base address (vector offset base, 0x0 at reset)
17	I_CTL	RW	IBox control (includes SDE, SBE, IC enable bits)
18	IC_FLUSH_ASM	WO	I-cache flush by ASM
19	IC_FLUSH	WO	I-cache flush all
20	PCTR_CTL	RW	Performance counter control
22	I_STAT	RW	IBox status
23	SLEEP	WO	Enter sleep mode
30	PCTX	RW	Process context (ASN, ASTER, ASTRR, FPE, PPCE fields)
43	CLR_MAP	WO	Clear register map (pipeline flush)

MBox IPRs (M):

Index	Mnemonic	Access	Description
32	DTB_TAG0	WO	DTB0 tag write (VA for TLB fill)
33	DTB_PTE0	WO	DTB0 PTE write (page table entry for TLB fill)
36	DTB_IS0	WO	DTB0 invalidate single (by VA)
37	DTB_ASN0	WO	DTB0 ASN write
38	DTB_ALTMODE	WO	DTB alternate mode (for PROBE instructions)
40	M_CTL	WO	MBox control
41	DC_CTL	WO	D-cache control
42	DC_STAT	WO	D-cache status
79	MM_STAT	RO	Memory management fault status
116:0	DTB_TAG1	WO	DTB1 tag write (dual DTB architecture)
116:1	DTB_PTE1	WO	DTB1 PTE write
116:4	DTB_IS1	WO	DTB1 invalidate single

CBox IPRs (C):

Index	Mnemonic	Access	Description
43	C_DATA	RW	CBox data register (serial shift interface)
44	C_SHFT	WO	CBox shift register control
192	CC	RW	Cycle counter
193	CC_CTL	WO	Cycle counter control

PAL-Managed IPRs (accessed via MFPR_*/MTPR_* PAL calls, not directly by index): ASN, ASTEN, ASTSR, ESP, FEN, IPL, KSP, MCES, PCBB, PRBR, PTBR, SCBB, SISR, SSP, SYSPTBR, TBCHK, USP, VPTB, WHAMI, PERFMON, DATFX. These are stored in IPRStorage_Hot and IPRStorage_Cold and accessed by PalService wrapper methods.

See Also: Chapter 20 – Boot Sequence, PAL, and SRM Integration (HW_MFPR/HW_MTPR implementation); 21264/EV6 Hardware Reference Manual, Chapter 5.