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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 20 – Boot Sequence, PAL, and SRM Integration > 20.5 Shadow Registers and HWPCB |
When PAL mode is entered, shadow registers are activated providing a separate register workspace for PAL code. PAL shadow registers substitute for R8–R14 and R25 during PAL mode execution. This allows PAL code to use these registers without saving/restoring the interrupted context's values — the hardware shadow bank automatically preserves the non-PAL register state.
Shadow registers are activated on enterPal() (m_shadowRegsActive = true) and deactivated on executeREI(). The execution engine checks the shadow register flag and routes register accesses to the appropriate bank. Shadow registers preserve state while the CPU is quiesced and enable efficient nested exception handling.
The HWPCB (HWPCB_core.h) is the per-CPU hardware process context block that holds the complete architectural state of a process. PAL entry captures full architectural state via saveContext() into the HWPCB, and HW_REI restores full architectural state via restoreContext() from the HWPCB. No partial restoration is permitted.
HWPCB fields include: the architectural PC, processor status (PS), current mode (CM), IPL, ASN, stack pointers for all four modes (KSP, ESP, SSP, USP), AST registers (ASTEN, ASTER, ASTRR, ASTSR), FP enable (FEN), PCBB (PCB base address), PTBR (page table base), SCBB (system control block base), VPTB (virtual page table base), PRBR, SYSPTBR, MCES, and exception state (EXC_ADDR, EXC_SUM).
HWPCBBank (globalHWPCBBank()) manages per-CPU HWPCB instances. It is initialized during system construction via globalHWPCBBank().init(numCpus). HWPCB state must be saved/restored across context switches (SWPCTX), and all four AST registers are part of process context.
The SWPCTX PAL call coordinates process context switching. It saves the current process state to the outgoing HWPCB, loads the incoming process state from the new HWPCB (pointed to by R16), updates the active PCBB, clears LL/SC reservations, and flushes per-process caches (PC and PA decode caches are flushed via IMB-equivalent behavior). ASN management during context switches uses the epoch-based lazy invalidation mechanism described in Chapter 17 — if the incoming process's ASN has a stale epoch, non-global TLB entries are invalidated.
See Also: HWPCB_core.h – HWPCB field definitions; 8.6 PAL Execution Model (shadow registers); 17.7 ASN Management and Coherence (epoch-based invalidation).