20.6 Privileged Instructions

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20.6 Privileged Instructions

The following instructions are legal only in PAL mode. Outside PAL mode, each generates an OPCDEC (illegal instruction) fault.

 

Instruction

Opcode

Function

HW_MFPR

0x19

Move From Processor Register — reads an IPR value into a general register. MFPR_* PAL calls are wrappers: write R0 with the IPR value read.

HW_MTPR

0x1D

Move To Processor Register — writes a general register value into an IPR. MTPR_* PAL calls are wrappers: read R16 as the value to write. Side effects include TLB invalidation, interrupt state updates, AST recalculation.

HW_LD

0x1B

Hardware Load — PAL-mode physical memory access bypassing normal VA→PA translation. Used by PAL code to read page table entries, HWPCB fields, and system data structures directly from physical memory.

HW_ST

0x1F

Hardware Store — PAL-mode physical memory write bypassing translation. Used by PAL code to update page table entries, HWPCB fields, and system control structures.

HW_REI

(within PAL)

Hardware Return from Exception/Interrupt — the sole legal exit from PAL mode. Restores context, deactivates shadow registers, flushes pipeline.

 

Privilege enforcement is multi-layered: instruction decode checks the PAL mode flag (PC bit 0 = 1), and any privileged instruction outside PAL raises an OPCDEC fault delivered precisely through the FaultDispatcher. Cache and TLB control operations (TBI, TBIS, DTB/ITB invalidation) are also restricted to PAL mode and routed through HW_MTPR with appropriate IPR-dispatch side effects.

 

See Also: 8.10 Enforcing the Privileged Boundary; 8.3 Privilege Levels.