ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9

The EMulatR SMP architecture provides correct, deterministic multiprocessor behavior that matches Alpha AXP specifications.

ExecutionCoordinator — SMP CPU management, CBox ownership, worker threads (416 lines)

MemoryBarrierCoordinator — global barrier synchronization, timeout detection (278 lines)

IPIManager — lock-free IPI message routing, atomic per-CPU slots (192 lines)

IPI_core — IPICommand enum (26 commands), encoding/decoding helpers (245 lines)

CPUStateManager — per-CPU execution state tracking (5 states)

ReservationManager — global LL/SC tracking, cross-CPU invalidation (153 lines)

Total: 1,284+ lines across SMP-specific headers (plus ReservationManager shared with Ch 5).

1.CPUs execute independently — each CPU runs in its own QThread with per-CPU pipeline, registers, TLBs, write buffers, and FaultDispatcher

2.Memory is shared but weakly ordered — one global GuestMemory, no visibility guarantees without barriers

3.Ordering is explicit — MB triggers global barrier coordination via IPIs; WMB is local-only

4.LL/SC is optimistic and globally tracked — ReservationManager scans all CPUs on every store commit

5.IPIs coordinate cross-CPU actions — 26 commands covering TLB invalidation, cache coherency, barriers, synchronization, and system control

6.PAL enforces safe transitions — sole authority for IPI handling, TLB shootdowns, context switches

7.Barriers ensure convergence — MemoryBarrierCoordinator with 2-second timeout and machine check on failure

8.No implicit global locks exist — all coordination uses atomic operations, lock-free IPI slots, and explicit barrier protocols

9.Exceptions and interrupts are per-CPU — strict isolation, cross-CPU effects only via explicit coordination

10.CPUStateManager tracks lifecycle — Running/Halted/Waiting/Quiesced/Reset per CPU

9.13 Summary