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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 18 – Fault Dispatcher & Precise Exceptions > 18.8 Precise Exception Guarantees |
When an exception is delivered, the following guarantees hold: all prior instructions have completed (every instruction older than the faulting instruction has retired through WB), the faulting instruction is identified (EXC_ADDR holds the faulting PC), no later instruction has executed (younger pipeline slots are invalidated), and architectural state is consistent (register files, memory, and IPRs reflect only committed results).
When delivering an exception from WB stage, the pipeline performs:
•flushYoungerSlots() — clears all instructions younger than the faulting instruction, preserving older instructions that have already committed
•Write buffers are drained if required (barrier-like behavior)
•LL/SC reservations are cleared via ReservationManager::breakReservation(cpuId)
•Speculative state is discarded (no speculative register writes survive)
•EXC_ADDR is set to the faulting PC
•Control transfers to PAL via enterPalMode()
The pipeline guarantees determinism: in-order retirement (m_instructionsRetired increments monotonically), one architectural commit per cycle, no speculative side effects (stores only commit in WB, registers only write in MEM via committed pending), and no privilege leakage.
Memory faults may occur during address translation (TLB miss), access permission checks, alignment checks, MMIO routing (unmapped PA), or bus errors. The MEM_STATUS enumeration in memory_core.h defines all possible return codes: Ok, OutOfRange, Misaligned, TlbMiss, AccessViolation, BusError, WriteProtected, TranslationFault, and others.
Faults are raised during the EX stage and prevent memory effects from committing. The PermissionDetail enumeration provides fine-grained fault classification for read, write, and execute permission failures at each privilege level, plus Fault-On-Write, Fault-On-Read, and Fault-On-Execute for demand-paging support.
Invariant: Faults prevent partial effects. No memory operation may partially commit. A faulting store never reaches SafeMemory. A faulting load never writes a result to the register file.
See Also: 15.11 Memory Fault Handling; 13.12 LL/SC and Determinism; memoryLib/memory_core.h – MEM_STATUS, PermissionDetail enumerations.