ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 7 - Exceptions, Faults, and Interrupts

The EMulatR exception system provides precise, deterministic exception handling that matches Alpha AXP architectural requirements.

FaultDispatcher — central event authority, per-CPU (449 lines)

PendingEvent — unified event structure (420 lines)

ExceptionFactory — event construction helpers (150 lines)

ExceptionClass_EV6 — 32-value exception classification enum

IRQPendingState — per-CPU interrupt tracking with atomic cross-thread safety (378 lines)

InterruptRouter — interrupt routing and IPI dispatch (505 lines)

Total: 1,932 lines across six exception system headers.

1.Faults are synchronous (detected in EX); interrupts are asynchronous (sampled between instructions)

2.All exceptions are precise — detect-early/deliver-late model ensures architectural consistency

3.Detection and delivery are decoupled — FaultDispatcher queues events and controls delivery timing

4.FaultDispatcher enforces priority and timing — flag-based fast path (eventPending() ~1 cycle), per-CPU, no atomics on hot path

5.PendingEvent is the universal event structure — carries classification, address context, fault details, interrupt specifics, and SMP metadata

6.Pipeline flushing ensures consistency — younger slots invalidated, write buffers drained, reservations cleared

7.PAL mode is the sole privileged handler — enterPalMode() saves context, sets EXC_ADDR, raises IPL to 7, enters kernel mode, flushes pipeline

8.IRQPendingState provides lock-free interrupt tracking — atomic summary bitmask, per-level source masks, cached highest pending level

9.Barriers guarantee exception safety — EXCB and TRAPB gate on FaultDispatcher state

10.SMP events (IPIs, TLB shootdowns) use the same delivery mechanism as device interrupts

7.13 Summary