<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 22 – Testing, Validation, and Architectural Compliance > 22.10 Known Deviations and Non-Goals

EMulatR explicitly documents its deviations from silicon behavior and its non-goals. These are documented choices, not omissions.

 

Simplified cache modeling: The emulator models coherency functionally, not microarchitecturally. Cache hit/miss timing is not simulated. Cache line fills are instantaneous. This simplification preserves correctness (coherency semantics are maintained) while eliminating complexity that would not improve architectural fidelity.

 

Synchronous FP execution: Floating-point operations execute synchronously in the EX stage. The pipeline stalls until the FP operation completes. No asynchronous FP completion tracking is used. This favors simplicity, correctness, and debuggability over throughput.

 

Simplified MMU timing: TLB lookups and page table walks complete within a single pipeline stage. Multi-cycle translation latency is not modeled. Translation correctness (address mapping, permission checking, fault generation) is fully implemented.

 

Partial SRM support: The SRM console implements the minimum command set required for boot and basic interaction. Full SRM firmware execution (complete ARC compatibility, all console commands, network boot) is deferred. CSERVE implements the six required selectors plus optional stubs.

 

PAL as C++ code: PAL is implemented as C++ methods, not as Alpha instructions in memory. This eliminates memory synchronization issues and simplifies debugging but means PALcode binary images are not loadable. This is a permanent architectural decision, not a temporary simplification.

 

Explicit non-goals: Cycle-exact microarchitectural timing, hardware-accurate cache timing (miss penalties, fill latencies), vendor-specific undocumented behavior, ARC console compatibility, host-specific optimizations that compromise determinism (JIT compilation, host SIMD acceleration), and silicon-level test modes.

 

See Also: 1.5 Non-Goals .