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The following are explicit non-goals. These constraints keep the system maintainable and verifiable.

 

•Cycle-perfect microarchitectural modeling of specific Alpha implementations (EV6, EV67, EV68 silicon differences are not modeled at the gate level)

•Out-of-order or speculative execution beyond architectural requirements

•Host-specific optimizations that compromise determinism (JIT compilation, host SIMD acceleration)

•Implicit or heuristic-based memory ordering (all ordering is explicit via barriers)

•Hardware-accurate cache timing or latency modeling

•Vendor-specific undocumented processor behavior

 

EMulatR claims architectural correctness when: architectural state transitions match Alpha AXP rules, exceptions are precise and ordered, memory ordering semantics are preserved, SMP interactions are race-free and deterministic, and privileged boundaries are enforced. It does not claim cycle-exact microarchitectural modeling or hardware-accurate cache timing. This distinction is intentional and explicit.

 

See Also: 1.2 Design Goals and Guiding Principles.