ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 1 - System Overview

EMulatR is structured into six conceptual layers. Each layer has a clearly defined responsibility and communicates with adjacent layers through explicit interfaces. No layer bypasses another's authority.

1.4.1 Execution Layer

The execution layer owns the per-CPU run loop and instruction lifecycle. It consists of AlphaCPU (the unit of execution), AlphaPipeline (the six-stage pipeline), PipelineSlot (per-stage instruction state), and instruction grains (the decoded instruction abstraction). Each AlphaCPU instance represents one physical Alpha processor with its own independent run loop, register files, and pipeline state.

1.4.2 Execution Domains (Boxes)

Execution is partitioned into six functional domains called Boxes. Each Box groups related architectural behavior and is invoked by grains during the Execute (EX) stage. Boxes are capability boundaries, not control boundaries — they do not own time, do not schedule instructions, and do not advance the pipeline.

•IBox – Instruction frontend (fetch, decode, grain resolution)

•EBox – Integer and address execution (ALU, conditional moves)

•FBox – Floating-point execution (IEEE 754, VAX compatibility)

•MBox – Memory operations (load/store, DTB translation)

•CBox – Coherency and serialization (barriers, write buffer, LL/SC)

•PalBox – Privileged execution (CALL_PAL, MFPR/MTPR, mode transitions)

1.4.3 Memory and Coherency Layer

The memory layer models Alpha's weakly ordered memory architecture. GuestMemory represents the shared physical address space and is the sole authority for physical memory visibility, LL/SC reservation invalidation, and SMP coherency effects. SafeMemory provides the backing store with bounds checking. The PTE/TLB subsystem handles virtual-to-physical translation with per-CPU ITB and DTB instances using SPAM (Set-Partitioned Address Mapping) structures.

1.4.4 Privilege and Control Layer

The privilege layer enforces Alpha's hardware-defined privileged execution environment. PAL (Privileged Architecture Library) is the sole authority for exception dispatch, interrupt dispatch, privileged register access (IPRs), context switching, and low-level SMP coordination. The FaultDispatcher queues and prioritizes all exceptional conditions. IPR storage provides dedicated registers for processor control state.

1.4.5 SMP Coordination Layer

The SMP layer manages multi-processor coordination. CPUs are created and identified by the SMP Manager within the ExecutionCoordinator. Each CPU has a unique CPUId with independent pipeline, registers, TLBs, write buffers, and LL/SC reservation state. Cross-CPU coordination occurs exclusively through GuestMemory (visibility and LL/SC invalidation), barriers (ordering enforcement), and IPIs (explicit signaling including TLB shootdown).

1.4.6 Device and MMIO Layer

The device layer models external hardware agents that participate in the memory system. Devices are memory-mapped, asynchronous, interrupt-driven, and strongly ordered at the MMIO boundary. The mmio_Manager routes accesses to registered IDeviceEmulator instances. DMA transfers are coordinated by the mmio_DMACoherencyManager. The controller stack implements a PCI bus model with SCSI host adapters and virtual storage devices.