ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 16 – Device Model & DMA > 16.11 Architectural Invariants (Normative)

The following invariants govern the device and DMA subsystem. Violation of any invariant constitutes an emulator bug.

MMIO Ordering: All MMIO accesses are strongly ordered — no reordering, no buffering, no speculation, no combining. MMIO writes bypass the write buffer and commit synchronously through GuestMemory → MMIOManager → device handler.

Device Asynchrony: Device emulators execute I/O operations asynchronously in dedicated threads. IDeviceEmulator::onRead() and onWrite() must return immediately and may never block on I/O. Long-running operations are queued to the device's I/O thread.

Endianness Transparency: The CPU and memory system never perform implicit byte swapping. All endianness conversion is the device emulator's responsibility. MMIOManager is byte-order-transparent.

DMA Routing: All DMA transfers route through GuestMemory with explicit AccessKind::DMARead or AccessKind::DMAWrite designation. No device may access SafeMemory directly. DMA writes must break overlapping LL/SC reservations.

Interrupt Delivery: Device interrupts are delivered via the coreLib/ IRQ system using atomic IRQPendingState bitmasks. The hot path (interrupt polling) is lock-free. All device interrupts enter PAL mode for dispatch.

Region Immutability: MMIO regions are registered during initialization and locked by MMIOManager::finalize(). No regions may be added, removed, or modified at runtime.

Device Independence: Device managers are independently instantiable and testable. No device category depends on another device category being functional. Degraded devices are recorded, not fatal.