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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 16 – Device Model & DMA > 16.3 Endianness and Device Registers |
All Alpha processors (21064, 21164, 21264/EV6) are natively little-endian. There is no big-endian mode switch. Memory is stored with the least significant byte at the lowest address. Instructions, data loads, and data stores all assume little-endian layout. Software that needs to manipulate big-endian data must perform explicit byte swapping using Alpha byte manipulation instructions (INSWL, EXTQH, MSKBL, etc.).
In EMulatR, the memory system (GuestMemory, SafeMemory) stores and retrieves values in little-endian format. The qFromLittleEndian() / qToLittleEndian() Qt helpers are used at the boundary between the emulator's native host byte order and the guest's little-endian expectation.
While the Alpha CPU is always little-endian, peripheral devices may present registers in either byte order. Real Alpha systems (AlphaServer, AlphaStation) handle this through I/O bridge and chipset configuration — the CPU always operates little-endian, but the I/O bridge can be configured for per-device endianness translation.
In EMulatR, endianness handling is the responsibility of the device emulator, not the CPU or memory system. The MMIOWindow structure carries a regEndian attribute (Little or Big) set during device registration. The contract is:
•The CPU always presents values in little-endian (host) order to MMIOManager
•MMIOManager passes the value unchanged to the device handler
•The device handler performs byte swapping if its registers are big-endian
•On read, the device handler returns the value in little-endian order to the CPU
This mirrors real hardware behavior: the I/O bridge (emulated by MMIOManager dispatch) delivers bytes in the format the CPU expects; the device controller handles its own internal byte order.
Device Type |
Register Endianness |
Notes |
|---|---|---|
SCSI HBA (KZPBA / QLogic) |
Little-endian |
PCI-native, matches Alpha byte order |
IDE Controller |
Little-endian |
ISA/PCI-native |
Network Interface (NIC) |
Big-endian (data path) |
Network byte order (big-endian) for packet data; control registers typically little-endian |
UART / Console |
Little-endian |
Byte-oriented, endianness is moot for 8-bit registers |
Fibre Channel HBA |
Big-endian (FC frames) |
FC frame headers are big-endian per FC-FS specification; control registers may vary |
Network adapters deserve particular attention: the NIC control registers (command, status, interrupt mask) are typically little-endian PCI registers, but the DMA data path carries Ethernet frames in network byte order (big-endian). The device emulator must handle both byte orders within the same device, swapping packet data buffers during DMA but not register values. Guest OS network drivers (e.g., the de driver under Tru64 or Linux/Alpha) expect this split behavior and use Alpha byte manipulation instructions to convert packet headers.
Invariant: The CPU and memory system never perform implicit byte swapping. Endianness conversion is always the device emulator's responsibility. MMIOManager is byte-order-transparent.
See Also: coreLib/mmio_core.h – MMIOWindow.regEndian attribute; Appendix: Endianness Rules (comprehensive implementation guide).