ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 1 - System Overview

This chapter provides a top-level architectural description of the EMulatR Alpha AXP emulator. It defines the major subsystems, their responsibilities, and how control and data flow through the system during execution.

EMulatR is a cycle-based, SMP-capable Alpha AXP processor emulator designed to faithfully reproduce the architectural behavior of DEC Alpha hardware running Tru64 UNIX. The emulator targets the EV6 (21264) family of Alpha processors and boots using authentic SRM console firmware images.

The system is structured around a clear separation between architectural specification and implementation:

•The Architecture (Chapters 1–11) defines what must be true: the execution model, pipeline contract, memory ordering rules, exception semantics, privilege boundaries, and SMP guarantees.

•The Implementation (Chapters 12–22) defines how those rules are enforced in code: the AlphaCPU worker, pipeline mechanics, Box implementations, memory subsystem, device models, fault dispatch, and boot sequence.

This document serves as the authoritative reference for the EmulatR project. It provides a navigable hierarchical structure that orients developers, maintainers, and reviewers, then directs them to the appropriate depth within this guide or the source code for detailed treatment.

This chapter is normative. The architectural invariants described here must be preserved by all implementations, refactors, and optimizations. The goal is not to explain individual instructions or implementation details, but to describe the shape of the system and the contracts between its components.

1.1 Purpose and Audience

1.1 Purpose and Audience