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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 21 – Debugging, Tracing, and Determinism > 21.5 Tracing by Subsystem |
Instruction tracing records: PC at fetch, decoded instruction (opcode, function, ra/rb/rc), grain identity (pointer from InstructionGrainRegistry), operand values (optional), result values, and retirement cycle via EXECTRACE_WB_RETIRE. Tracing granularity is configurable: fetch-level (records all fetched instructions including flushed), execute-level (records instruction execution outcomes), or retirement-level (records only architecturally committed results). Tracing may be continuous, conditional (filtered by PC range, opcode class, or CPU), or event-triggered.
Pipeline tracing observes: slot occupancy across the six stages (IF → DE → IS → EX → MEM → WB), stall reasons (barrier engagement, hazard detection, memory wait), barrier engagement and release events (CBox logs barrier kind, stall entry, and release cycle), flush events via EXECTRACE_PIPELINE_FLUSH (caller name, current PC, flush reason), and branch misprediction recovery. This is critical for diagnosing deadlocks, verifying barrier correctness, and understanding stall behavior.
The FaultDispatcher integrates deeply with the tracing infrastructure. Traceable events include: fault creation (ExceptionFactory method called, ExceptionClass assigned), priority arbitration (when multiple events pending), deliverability decisions (event reaches WB, slot.faultPending checked), PAL vector selection (ExceptionMapping_inl::mapClassToPalVector, PalVectorTable lookup), PAL mode entry (EXECTRACE_PAL_ENTRY with PalEntryReasonTrace), and HW_REI restoration (EXECTRACE_PAL_EXIT). Each exception is traceable to the exact faulting instruction, exact architectural state, and exact cycle.
Interrupt tracing records: IRQ assertion (device thread raises interrupt via raiseInterrupt()), masking decisions (current IPL vs pending level), delivery cycle (when claimNext() succeeds), PAL entry (EXECTRACE_INTERRUPT), and handler completion (HW_REI). IPI tracing includes: sender CPU, target CPU(s), IPICommand payload type, encoded parameter (VA/ASN), acknowledgment timing, and IPIManager per-CPU statistics (totalCount). This is essential for SMP debugging — IPI-related bugs are often the hardest to diagnose without comprehensive tracing.
Memory tracing supports: load/store address, size, and data values, write buffer enqueue and drain events, barrier-forced drain sequences, LL/SC reservation creation (setReservation() with cache line address and CPU ID), reservation invalidation (breakReservationsOnCacheLine() with triggering CPU and address), STx_C success/failure outcomes, and MMIO reads/writes with CPU ID. False sharing and livelock scenarios are explicitly observable through reservation tracing — every creation and invalidation event is logged with the responsible CPU and cache line address.
See Also: Chapter 18 – Fault Dispatcher & Precise Exceptions (fault event tracing); Chapter 19 – Interrupt Architecture & IPI (IPI tracing); Chapter 15 – Memory System Implementation Details (memory and reservation diagnostics).