<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 12 – AlphaCPU Core > 12.9 SMP Awareness

Each AlphaCPU knows its CPUId (m_cpuId, assigned at construction), participates in SMP coordination via injected references (m_reservationManager, m_ipiManager, m_memoryBarrierCoordinator), receives IPIs as interrupts (via m_pending/m_router), and performs local TLB invalidation via handleTLBShootdownIPI().

 

handleTLBShootdownIPI(cpuId, ipiData) decodes the IPICommand from the IPI data and dispatches to the appropriate TLB invalidation: TLB_INVALIDATE_VA_ITB → m_tlb→invalidateTLBEntry(cpuId, Realm::I, va, asn), TLB_INVALIDATE_VA_DTB → Realm::D, TLB_INVALIDATE_ASN → m_tlb→invalidateTLBsByASN(cpuId, asn), TLB_INVALIDATE_ALL → m_tlb→invalidateAllTLBs(cpuId).

 

AlphaCPU never directly modifies another CPU's state. All cross-CPU effects occur through IPIs (which the target CPU processes in its own run loop) or through shared state (ReservationManager, GuestMemory) with proper atomic operations.

 

See Also: Chapter 9 - SMP Architecture.