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The Alpha AXP architecture is weakly ordered. The emulator preserves this property intentionally.

 

Core design principles:

•GuestMemory provides no inherent ordering — it is a flat physical address space with no implicit sequencing

•Loads complete synchronously — data is returned immediately during EX stage

•Stores are deferred via write buffers — they become visible asynchronously

•Ordering is enforced only by barriers — MB, WMB, EXCB, TRAPB

•MMIO is strongly ordered by design — no buffering, no reordering, no speculation past MMIO regions

•Correctness is prioritized over speculative complexity

 

Memory correctness is achieved through explicit serialization, not implicit sequencing. This mirrors the Alpha AXP specification and ensures that software written for Alpha's weak memory model behaves correctly.

 

See Also: 5.10 Memory Barriers (preview); Chapter 6 - Serialization and Stall Model.