<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.3 Memory Layers Overview

The memory system is structured into distinct layers, each with a clear responsibility. No layer performs hidden work on behalf of another.

 

Virtual Address (VA)

 │

 ▼

Translation (ITB / DTB via Ev6Translator)

 │

 ▼

Physical Address (PA)

 │

 ▼

┌───────────────────────────────────┐

│ GuestMemory                       │

│ (PA Router + Reservation Tracker) │

│                                   │

│ ┌────────────┐ ┌───────────────┐  │

│ │ SafeMemory │ │ MMIO Manager  │  │

│ │ (RAM)      │ │ (Devices)     │  │

│ └────────────┘ └───────────────┘  │

└───────────────────────────────────┘

 

The layer responsibilities are:

 

Ev6Translator — converts virtual addresses to physical addresses using ITB (instruction) and DTB (data) translation buffers, with page table walking on TLB miss. Per-CPU, supports ASN tagging, KSEG fast-path, and canonical address checking.

 

GuestMemory — the single shared physical address space visible to all CPUs. Routes physical addresses to the correct subsystem (SafeMemory, MMIO) via a PA routing table. Also hosts LL/SC reservation tracking.

 

SafeMemory — implements actual physical RAM storage. Byte-addressable, bounds-checked, thread-safe, deterministic. Uses SparseMemoryBacking for on-demand page allocation.

 

MMIO Manager — maps physical address ranges to registered device emulators (IDeviceEmulator). Strongly ordered.

 

See Also: Sections 5.4–5.7 for individual layer detail.