<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 5 - Memory System Architecture > 5.1 Purpose of This Chapter

This chapter defines the memory architecture of EMulatR. It explains how memory is modeled, accessed, translated, ordered, and shared across CPUs in both uniprocessor and SMP configurations.

 

This chapter clarifies:

•What "memory" means inside the emulator — the layered architecture from virtual addresses to physical backing

•How virtual addresses become physical accesses — the Ev6Translator and page table walker

•Where ordering does not exist by default — the weak ordering model

•Where ordering is enforced — barriers and MMIO strong ordering

•How memory interacts with the pipeline, Boxes, and SMP

•The physical address routing table — how GuestMemory dispatches to SafeMemory, SRM firmware, and MMIO

 

This chapter is architectural, not instruction-specific. Barrier mechanics are defined in Chapter 6 — Serialization and Stall Model. Implementation-level memory code is documented in Chapter 15 — Memory System Implementation Details.

 

See Also: Chapter 6 - Serialization and Stall Model; Chapter 15 – Memory System Implementation Details.