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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 15 – Memory System Implementation Details > 15.5 Load and Store Semantics |
All loads in EMulatR complete synchronously during the EX stage. The MBox calls GuestMemory::readRouted() (or the typed wrappers read8/16/32/64), which classifies the PA, routes to SafeMemory or MMIOManager, and returns data and a MEM_STATUS code immediately. There is no speculative or deferred load completion. A completed load reflects architectural memory state at that moment, subject to write buffer forwarding and ordering rules.
Stores do not immediately update SafeMemory. Instead, the CBox enqueues each store into a per-CPU write buffer via WriteBufferManager::addEntry(). The WriteBufferEntry structure records the physical address, data, access size (1/2/4/8), a validity flag, an MMIO flag, and a timestamp for ordering enforcement. Write buffers drain asynchronously; memory barriers control when stores become globally visible.
A store becomes architecturally visible when it drains from the write buffer and is committed to SafeMemory (or dispatched to the MMIOManager for MMIO writes). This models Alpha's weak memory ordering faithfully.
Invariant: A store may retire from the pipeline before it becomes globally visible. Loads are synchronous; stores are buffered.
See Also: coreLib/WriteBufferEntry.h (~67 lines) – Write buffer entry structure; 14.5 CBox – Cache / Control Box; 15.6 Write Buffer Implementation.