<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 9 - SMP Architecture > 9.2 SMP Design Philosophy

EMulatR follows five core SMP principles:

 

1.True symmetry — all CPUs are peers. There is no "master" CPU. Any CPU can boot, handle interrupts, or execute PAL code.

2.Per-CPU execution, shared memory — each CPU runs independently in its own thread but observes a shared physical address space (one global GuestMemory instance).

3.Weak ordering by default — memory ordering is not implied across CPUs. Without explicit barriers, a store on CPU 0 may be observed at any time (or never) by CPU 1.

4.Explicit synchronization — ordering and coordination occur only through defined mechanisms: barriers (MB/WMB), IPIs, PAL operations, and atomic instructions (LL/SC).

5.Deterministic correctness over speculative cleverness — the emulator prioritizes verifiable correctness over performance optimization, making SMP behavior observable and debuggable.

 

See Also: 5.2 Design Philosophy (weak ordering).