9.1 Purpose of This Chapter

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9.1 Purpose of This Chapter

This chapter defines how EMulatR implements symmetric multiprocessing (SMP) while preserving Alpha AXP architectural guarantees.

 

SMP is not an add-on. It affects memory visibility, exception delivery, atomic operations, interrupt routing, PAL behavior, and serialization. This chapter explains:

•How CPUs are instantiated and identified — ExecutionCoordinator, CPUWorker, CPUStateManager

•What state is per-CPU vs shared

•How CPUs coordinate — IPIManager, MemoryBarrierCoordinator

•How ordering is enforced across CPUs — global barriers, IPI-driven convergence

•How correctness is preserved without global locking

 

See Also: Chapter 5 - Memory System Architecture (shared GuestMemory); Chapter 6 - Serialization and Stall Model (barrier SMP semantics); Chapter 8 - PAL and Privileged Boundary (PAL SMP role).