ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 15 – Memory System Implementation Details > 15.13 Architectural Invariants (Normative)

The following invariants are normative. Violating any invariant breaks Alpha architectural correctness.

•GuestMemory is globally shared. One unified physical address space; all CPUs, DMA, and devices route through the same GuestMemory instance.

•SafeMemory is storage only. It never enforces architecture rules, never knows physical addresses, and never participates in ordering.

•Loads are synchronous. A completed load reflects architectural memory state at that moment.

•Stores are buffered. A store may retire before it becomes globally visible.

•MMIO is strongly ordered. MMIO accesses are never buffered, execute synchronously, and cannot be reordered.

•Barriers serialize visibility. Memory barriers do not perform I/O; they stall the pipeline until ordering conditions are satisfied.

•LL/SC never blocks. Reservations are optimistic — they succeed or fail but never stall.

•Faults prevent partial effects. No memory operation may partially commit.