<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 6 - Serialization and Stall Model > 6.13 Serialization in SMP Systems

In EMulatR SMP configurations, serialization has cross-CPU implications:

•Each CPU has local write buffers — MB/WMB drain the local buffer first

•MB may require global coordination — CBox::RequestMemoryBarrier() forwards to the global MemoryBarrierCoordinator, which may send IPIs to all other CPUs

•WMB is local only — it drains the local write buffer without global coordination, making it significantly cheaper than MB

•PAL serialization coordinates globally — issueMemoryBarrier() with MemoryBarrierKind::PAL initiates a global barrier and waits for all CPU acknowledgments

•IPIs may be used to enforce ordering — cross-CPU TLB invalidations, barrier acknowledgments

•CBox state machine — transitions from RUNNING to SERIALIZING during barrier processing, back to RUNNING on release

 

Barriers ensure that all CPUs converge to a consistent memory view. Without barriers, CPUs may observe memory changes from other CPUs in any order — this is by design and matches the Alpha AXP specification.

 

See Also: 5.14 SMP Considerations; Chapter 9 - SMP Architecture.