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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 6 - Serialization and Stall Model > 6.14 Summary |
The EMulatR serialization model preserves Alpha AXP's explicit ordering semantics while providing clear, debuggable barrier mechanics.
1.Alpha is weakly ordered by default — no instruction implies ordering unless it is a barrier
2.Ordering is explicit, never implicit — barriers are the only mechanism for enforcing visibility
3.Barriers stall the pipeline — they do not execute work, they gate completion
4.MB orders all memory operations — drains local write buffers and coordinates globally in SMP
5.WMB orders stores only — local drain, no global coordination, lighter than MB
6.EXCB and TRAPB enforce precise exception/trap semantics — EXCB waits for all prior stages to clear and all events to deliver; TRAPB waits for arithmetic trap resolution
7.CALL_PAL is the strongest serialization point — MB + EXCB + pipeline flush + reservation clearing
8.Serialization is essential for SMP correctness — barriers ensure all CPUs converge to a consistent view
9.MemoryBarrierKind enumerates 13 barrier/hint types — from TRAPB (0x0000) through PAL (0xFFFF)
10.Pipeline stall/release is mechanical — flag-based in stage_MEM(), release via advance() and checkBarrierRelease()
See Also: Chapter 7 - Exceptions, Faults, and Interrupts (next chapter).