<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 7 - Exceptions, Faults, and Interrupts > 7.1 Purpose of This Chapter

This chapter defines how the EMulatR emulator detects, prioritizes, delivers, and resolves exceptions, faults, and interrupts while maintaining precise architectural state.

 

Alpha AXP enforces precise exceptions: when an exception is taken, all prior instructions have completed, and no later instruction has modified architectural state.

 

This chapter explains:

•The classification of exceptional events — faults, traps, interrupts, machine checks

•Where exceptions are detected and how they are queued

•The FaultDispatcher: central authority for event management

•Priority ordering and delivery timing

•How pipeline state is preserved or discarded

•How PAL mode is entered on exception delivery

•The interrupt subsystem — IRQPendingState, InterruptRouter, IPIs

 

See Also: Chapter 6 - Serialization and Stall Model; Chapter 8 - PAL and Privileged Boundary; 3.14 Precise Exceptions.