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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 8 - PAL and Privileged Boundary > 8.2 What PAL Is (and Is Not) |
PAL is a hardware-defined privileged execution mode. It is the sole authority for exception dispatch, interrupt dispatch, privileged register access (IPRs), context switching primitives, and low-level SMP coordination. PAL code executes using normal Alpha instructions inside the normal pipeline, but under strictly elevated privileges. It is entered only through architecturally defined vectors.
PAL is not microcode, not a firmware blob that runs outside the pipeline, not a device driver layer, not a replacement for the operating system, and not a software trap handler. PAL is part of the architectural contract — it defines the interface between hardware and the operating system.
In EMulatR, PAL is implemented as C++ code executed through PalService methods, not as a memory region. CALL_PAL instructions execute C++ handlers via PalBoxBase → PalService delegation. There is no PAL code stored in memory — this is a deliberate design choice that eliminates an entire class of memory synchronization issues.
See Also: 4.9 PalBox - Privileged Architecture Library Box (PalService delegation model).