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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 6 - Serialization and Stall Model > 6.2 Weak Ordering as the Default |
By default, the Alpha AXP memory model is weakly ordered. The emulator intentionally preserves this behavior:
•Loads may reorder with other loads
•Loads may reorder with stores
•Stores may reorder with other stores
•Stores may be deferred via write buffers
•Other CPUs may observe memory changes at indeterminate times
No instruction implies ordering unless explicitly defined as a barrier.
Without serialization, the following outcomes are architecturally legal:
•A store may not be visible to other CPUs immediately
•A later load may observe stale data
•Device registers may be accessed out of protocol order
•LL/SC sequences may fail unexpectedly
•Exceptions may observe inconsistent state
These outcomes are prevented only by explicit barriers. The emulator does not add implicit ordering that the hardware would not provide.
See Also: 5.2 Design Philosophy (weak ordering).