ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 2

The EMulatR execution model is:

•Cycle-based and deterministic — one iteration equals one hardware cycle

•Pipeline-driven with explicit serialization — barriers and PAL entry are the only ordering mechanisms

•Precise in exception and interrupt delivery — all prior instructions complete before delivery

•SMP-safe by design — no implicit coordination, no shared internal state

•Conservative in speculation — speculation stops at barriers, PAL entry, and serialization points

1.One run-loop iteration equals one hardware cycle

2.The pipeline is the engine of execution — AlphaCPU drives it, does not bypass it

3.The EX stage performs all architectural work — other stages are bookkeeping

4.WB is the only commit point — anything before WB may be safely discarded

5.Stalls and barriers are explicit, not implicit — every stall has a defined release condition

6.Speculation stops at barriers and PAL entry — no speculative privilege leakage

7.Register writes in MEM, reads in EX — the backward stage ordering provides the forwarding path

This model provides a stable foundation for instruction execution, memory ordering, and system-level coordination.

2.10 Summary