<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.3 Translation Path

17.3.1 Where Translation Occurs

 

Address translation occurs in MBox during the EX stage. The Ev6Translator (pteLib/ev6Translation_struct.h, ~1,336 lines) provides the translation engine. Translation responsibilities include VA→PA conversion, ITB/DTB miss detection, access violation detection, alignment fault detection, and precise translation fault raising.

 

Translation never occurs during fetch (IBox translates instruction addresses separately via the ITB), decode, or writeback. The MBox calculates the effective address via calculateEffectiveAddress(slot) — Rb + SEXT(displacement) — and then invokes the translator.

 

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17.3.2 Fast Translation Path

 

ev6TranslateFastVA() is the primary translation entry point, optimized for the common case:

 

ev6TranslateFastVA(cpuId, va, asn, accessType)

 │

 ├── 1. Canonical address check

 │ (bits above vaBits-1 must sign-extend)

 │ Fail → TranslationResult::NonCanonical

 │

 ├── 2. KSEG fast-path check

 │ (kernel segment direct mapping, no TLB needed)

 │ Hit → PA = VA & ksegMask, return Success

 │

 ├── 3. TLB lookup via Ev6SiliconTLB

 │ Construct tag: VPN = VA >> pageShift

 │ Search per-CPU SPAM shard

 │ Hit → check permissions (KRE/KWE/URE/UWE vs mode)

 │ check FOE/FOW/FOR

 │ PA = (PFN << pageShift) | (VA & offsetMask)

 │ return Success

 │

 └── 4. TLB miss

 return TranslationResult::TlbMiss

 (caller decides whether to walk or raise fault)

 

The fast path does not walk page tables. On TLB miss, it returns TlbMiss immediately, leaving the miss handling decision to the caller (typically MBox or PAL).

 

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17.3.3 Full Translation Path

 

ev6TranslateFullVA() performs the same checks as the fast path, plus a full page table walk on TLB miss using the three-level Alpha page table structure (L1→L2→L3). The walk reads PTEs from GuestMemory at each level, checking validity at each step. On successful walk, the resulting PTE is inserted into the TLB via Layer 1 and the translation succeeds. On failure at any level, the appropriate TranslationResult is returned:

 

 

See Also: pteLib/ev6Translation_struct.h (~1,336 lines) – Ev6Translator; pteLib/calculateEffectiveAddress.h – EA calculation helper; 14.4 MBox – Memory Box.