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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.4 SPAM TLB Cache Architecture |
SPAM (Set Prediction and Access Memory) is the name for the per-CPU PTE cache in EMulatR. It models the Alpha EV6 Translation Lookaside Buffer as a sharded, set-associative cache with per-CPU isolation. The SPAM cache acts like a 4-dimensional associative array indexed by CPU, Realm (ITB/DTB), SizeClass, and BucketIndex.
SPAMShardManager (pteLib/alpha_spam_manager.h) implements sharding along four axes:
By CPU: Each logical CPU receives its own slice of the TLB cache. CPU 0's SPAM shard is fully independent of CPU 1's shard. This eliminates cross-CPU contention on the translation hot path.
By Realm: Separate shards are maintained for Instruction translation (ITB) and Data translation (DTB). This reflects the EV6 hardware, which has physically separate ITB and DTB structures.
By Size Class: When ShardBySize=true, entries are grouped by page size (e.g., 8K, 64K). This supports granularity hint (GH) superpages without polluting the base-page-size buckets.
By Bucket Index: Each shard subdivides its set into hash buckets for fast lookup. The VPN and ASN are hashed to select a bucket, and within the bucket, a set-associative search finds the matching entry.
Per-CPU SPAM Layout:
┌────────────────────────────┐
│ CPU 0 CPU 1 CPU 2 ... │
│ ┌──────┐ ┌──────┐ ┌──────┐ │
│ │ ITB │ │ ITB │ │ ITB │ │
│ │ DTB │ │ DTB │ │ DTB │ │
│ └──────┘ └──────┘ └──────┘ │
└────────────────────────────┘
SPAMBucket (pteLib/alpha_spam_bucket.h) is the storage unit within each shard. It holds a fixed-associativity set of PTE entries and provides lookup, insert, and invalidate operations within that set. Each bucket entry stores an Ev6TLBTag (VPN, realm, sizeClass, matchAllASNs flag), the ASN, the validity state, and the PTE content (AlphaPTE via traits).
On lookup, the bucket performs a linear scan of its entries, matching VPN, ASN (or global flag), realm, and size class. On insert, the bucket uses the configured replacement policy to select a victim entry if the set is full.
The primary operations exposed by SPAMShardManager:
Operation |
Description |
|---|---|
tlbLookup(cpuId, tag, asn) |
Search per-CPU shard for matching TLB entry; returns pointer to entry or null |
tlbInsert(cpuId, tag, asn, pte) |
Insert PTE into per-CPU shard; uses replacement policy for victim selection |
invalidateASN(cpuId, asn) |
Invalidate all entries for a specific ASN on one CPU |
invalidateASN_AllShards(asn) |
Invalidate ASN across all CPUs (SMP-wide) |
tbis(cpuId, va, asn) |
Invalidate single VA entry (TBIS — TLB Invalidate Single) |
tbia(cpuId) |
Invalidate all entries on one CPU (TBIA — TLB Invalidate All) |
Configuration parameters include number of buckets, associativity (entries per bucket), maximum ASNs, and replacement policy selection. The maintenanceTick() method performs periodic cache sweeps and telemetry collection.
See Also: pteLib/alpha_spam_manager.h – SPAMShardManager template; pteLib/alpha_spam_bucket.h – SPAMBucket template; 9.4 Per-CPU vs Shared State .