|
<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.5 Ev6SiliconTLB and Layer Architecture |
The translation subsystem enforces strict layering to maintain separation of concerns:
Layer 0 — Silicon (SPAMShardManager): Provides raw TLB storage and lookup. Knows nothing about page tables, miss handling, or page table walks. Operates purely on tags, ASNs, and PTE entries. This layer is accessed only through Layer 1.
Layer 1 — TLB Interface (Ev6SiliconTLB, Ev6TLBInterface): Wraps Layer 0 with a clean lookup/insert/invalidate API. No traits, no page-table knowledge. This is the layer that MBox, PAL, and IBox call for translation operations. The Ev6SiliconTLB is instantiated as a singleton via Ev6SiliconTLB_Singleton::initialize(cpuCount, cfg) during emulator boot.
Layer 2 — PAL / MMU / Miss Handling: On TLB miss, this layer performs the three-level page table walk via walkPageTable_EV6(), reading PTEs from GuestMemory at each level. On success, it calls Layer 1 insert to refill the TLB. On failure, it raises the appropriate translation fault (TNV, FOE, FOW, FOR) through the FaultDispatcher.
Layer 2: PAL / MMU / Miss Handler
│ walkPageTable_EV6() raise TNV/FOE/FOW/FOR
│ GuestMemory PTE reads FaultDispatcher
▼
Layer 1: Ev6TLBInterface / Ev6SiliconTLB
│ lookup() insert() invalidate()
▼
Layer 0: SPAMShardManager / SPAMBucket
│ Per-CPU shards, hash buckets, replacement policies
▼
PTE entry storage (AlphaPTE via PTETraits)
Ev6SiliconTLB_Singleton (pteLib/Ev6SiliconTLB_Singleton.h) provides process-wide access to the TLB subsystem. Initialization occurs once at emulator boot:
Ev6VMConfig cfg{};
cfg.basePageSize = systemConfig.vm.pageSize; // 8K, 16K, 32K, 64K
cfg.enableSuperpage64K = systemConfig.vm.enable64K;
Ev6SiliconTLB_Singleton::initialize(cpuCount, cfg);
After initialization, the SPAM shard manager is accessed via Ev6SiliconTLB_Singleton::instance().spam(). The Ev6SiliconConfig class centralizes page size configuration (basePageSize, superpage options) and is fed from the system configuration loader.
The EV6 implementation uses two Data Translation Buffer banks (DTB0 and DTB1), reflecting the real EV6 hardware's dual-pipe TLB design. The DualDTBManagerInterface (pteLib/DualDTBManagerInterface.h) defines DTB0/DTB1-specific operations: separate lookup, insertion, invalidation, and occupancy queries for each bank. The ev6_DtbPteTempRegister helpers manipulate the EV6 DTB PTE Temporary Register used during DTB miss handling.
This dual-bank design allows the EV6 to walk PTEs in parallel with execution — one pipe can service a DTB miss while the other continues executing non-memory instructions.
See Also: pteLib/Ev6SiliconTLB_Singleton.h – TLB singleton; pteLib/DualDTBManagerInterface.h – Dual DTB interface; 14.4 MBox – Memory Box (translation initiation).