<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 22 – Testing, Validation, and Architectural Compliance > 22.4 Exception and Fault Validation

Exception correctness is validated by triggering known fault conditions and verifying the complete delivery chain:

 

Correct exception class: Each fault condition must produce the expected ExceptionClass_EV6 value. An unaligned access must produce Unalign, not Dfault. A privileged instruction in user mode must produce OpcDec.

 

Precise delivery point: The faulting instruction is identified exactly (EXC_ADDR = faulting PC). No younger instruction commits. All prior instructions have completed. Architectural state is consistent at the delivery point.

 

Correct PAL vector selection: ExceptionMapping_inl::mapClassToPalVector() maps to the expected PalVectorId_EV6. The PalVectorTable lookup produces the correct PAL entry PC.

 

Correct state on PAL entry: EXC_ADDR contains the faulting PC. EXC_SUM is populated for arithmetic exceptions. PS reflects the pre-exception state. IPL = 7, CM = KERNEL, shadow registers active.

 

Key invariants tested: No younger instruction commits (flushYoungerSlots verified), no partial memory effects survive (faulting store never reaches SafeMemory, faulting load never writes result register), LL/SC reservations are cleared on delivery, and HW_REI restores state exactly (full register-context vector copy verified).

 

See Also: Chapter 18 – Fault Dispatcher & Precise Exceptions (delivery mechanics under validation).