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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.18 Summary |
The AlphaPipeline in EMulatR is in-order, execute-centric, deterministic, precisely serialized, and SMP-safe by design.
1.Six-stage pipeline with lightweight stages — only EX and WB perform real work
2.EX stage performs all architectural work — via grain->execute(slot)
3.WB is the only commit point — store commits, fault dispatch, retirement
4.MEM is a forwarding stage — commitPending() writes registers before EX reads them
5.Backward advancement (WB → IF) prevents hazards and enables forwarding
6.Ring buffer implementation — six PipelineSlots with rotating m_head pointer
7.FP execution stalls EX synchronously — no asynchronous completion tracking
8.Stalls and serialization are explicit — every stall has a defined release condition
9.Precise exceptions are guaranteed — detected in EX, delivered in WB
10.Grain caching — decode once, execute many times via InstructionGrainRegistry
See Also: Chapter 4 - Functional Execution Domains ("Boxes) (next chapter).