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--- 16KPage 32-bit 32BitInstruction 32KPage 64-bit 64ByteAlignment 64KPage 8KPage Acceleration Access AccessControl AccessFault AccessIntent (enum) Accessor AccessPerm (enum) AccessPermissions AccessRouting AccessType AccessValidation AccessViolation Accuracy Acknowledge Interrupt acknowledgedCpus Acknowledgment Acquisition ActiveCPUCount ActiveStackPointer actualTarget ACV ACV_FAULT Adapter ADD Add64 addCarry Addition ADDL ADDLV ADDL-V addOverflow addOverflow_fast addQ ADDQV Address Address Space Number address space partitioning address space sharding AddressCalculation AddressClassification AddressComputation AddressOrdering AddressRange AddressRouting AddressSpace address-space AddressSpaceMatch AddressSpaceNumber AddressStride AddressTranslation ADDS ADDT advance Advanced Usage Advancement advancePC AdvanceResult advanceRing AdvanceSignal Alignment ALIGNMENT_FAULT AlignmentCheck AlignmentFault Allocation Alpha Alpha AXP Alpha AXP architecture Alpha AXP emulator Alpha hardware fidelity alpha_pte_core alpha_pte_core.h alpha_pte_traits alpha_pte_traits.h alpha_pte_traits_ev6_dtb alpha_pte_traits_ev6_dtb.h alpha_pte_traits_ev6_itb alpha_pte_traits_ev6_itb.h alpha_pte_view alpha_pte_view.h alpha_spam_bucket.h alpha_spam_manager.h Alpha21064 Alpha21164 Alpha21264 AlphaArchitecture AlphaAXP AlphaAXP_LL_SC AlphaAXPArchitectureReferenceManual AlphaCPU AlphaCPU core AlphaCPU Integration AlphaCPU interrupt polling, CPU Integration AlphaCPU worker AlphaCPUInstance AlphaCPUIntegration AlphaImmediate AlphaPipeline AlphaPlatform AlphaPTE AlphaPTE (struct) AlphaServer AlphaSSE AlwaysInline AMASK AMOVRM AMOVRR AND ANSI API Appendix Architectural Architectural barriers Architectural behavior reproduction Architectural correctness Architectural description Architectural fidelity Architectural invariants Architectural invariants referenc Architectural semantics Architectural specification Architectural visibility ArchitecturalActivity ArchitecturalBoundary ArchitecturalCommit ArchitecturalCondition ArchitecturalConsistency ArchitecturalConstant ArchitecturalContract ArchitecturalCorrectness ArchitecturalDrift ArchitecturalEffect ArchitecturalFault ArchitecturalFlag ArchitecturalGuarantee ArchitecturalLayer ArchitecturalMode ArchitecturalOffset ArchitecturalOrdering ArchitecturalPC ArchitecturalProfile ArchitecturalRequirement ArchitecturalRule ArchitecturalSemantics ArchitecturalSerialization ArchitecturalSideEffect ArchitecturalState ArchitecturalValue ArchitecturalVector ArchitecturalVisibility Architecture Architecture chapters (1–11) arg ARITH Arithmetic ArithmeticException Arithmetic-Legacy ArithmeticShift ArithmeticTrap ArithmeticTrapFlag ASA ASA_EmulatR ASA_EmulatR_ini ASAEmulatr.ini asL ASM ASN ASN (Address Space Number) ASN_MAX ASNChange asnGenAtFill ASN-scoped invalidation, IPI Integration ASNType asQ Assertions Assignment Assume AST AST Enable Register AST Summary Register ASTDelivery ASTEN ASTEnable ASTER astMode ASTRequest ASTRR ASTSR ASTState ASTThreshold Asynchronous Interrupt AsynchronousDevice AsynchronousEvent Asynchrony Atomic atomic pending IPL mask, Architecture AtomicBoundary AtomicCorrectness AtomicFailureSemantics AtomicFence AtomicIsolation Atomicity AtomicOperation AtomicPagePointer AtomicReservation AtomicSemantics AtomicSequence AtomicState Attribute Attribution Audience Authoritative reference Authority AutomaticCleanup AXP AXP_ALWAYS_INLINE AXP_DEBUG AXP_HOT AXPAttributes axpsnap Backend BackingStore BackingStoreMapping Backpressure Backward BackwardAdvancement BackwardPipelineAdvance BAR Barrier Barrier_EXC Barrier_MB Barrier_NONE Barrier_TRAP Barrier_WRITE BarrierBlock BarrierCoordination BarrierCoordinator BarrierInitialization BarrierInstruction BarrierInteraction BarrierKind BarrierMechanics BarrierRelease BarrierReleaseCondition BarrierRequest barriers BarrierSemantics BarrierSerialization BarrierSetup BarrierStall BarrierStateMachine BarrierSynchronization BarrierType base BaseAddress BaseAddressRegister baseline policy BasePageSize Batch Behavior Below is a consolidated architectural mnemonic list (Alpha AXP base ISA, representative full set), one mnemonic per line, no commentary. BEQ BGE BGT BHT BIC bifurcate BigEndianData Bimodal bin BIS BIST bitExtension Bitfield Bitmap BitMask bitScan Bitset Bitwise BIU BLBC BLBS BLE BLT BNE Bookkeeping boot Boot sequence bootPC BootService Borrow Boundaries Boundary BoundaryReference BoundsChecking Box Boxes BoxResult BPMode BP-mode BPT BR Branch BranchCondition BranchEvaluation branchImmediate BranchMisprediction BranchOutcome BranchPrediction branch-prediction BranchPredictor BranchPredictor.h BranchResolution BranchReturn BranchStrategy branchTaken branchTarget breakAllReservations BreakPoint breakReservation breakReservationsOnCacheLine Broadcast broadcast invalidation broadcast invalidation, IPI Integration broadcast IPI, IPI Integration BSR BTB Bubble bucket bucket index BucketCount bucketed lookup Buffer BufferDrain Buffering Bug BUGCHECK BUGCHK BuildConfiguration BulkAccess BulkOperation bumpAll bumpBoth bumpDTB bumpGlobal bumpITB BusError BusyState BWT Bypass BypassMode Byte ByteAddressability ByteManipulation ByteOperation ByteOps ByteSwapLayer C_DATA C_SHFT C++17 cache cache access pattern cache configuration cache consistency cache entry cache eviction cache flags cache flush sharding cache hit cache invalidation sharding cache isolation cache locality cache management cache miss cache parallelism cache partitioning cache replacement cache scalability cache sharding cache subset CacheCoherency CacheControl cache-eviction cache-flush CacheHint CacheHit CacheLine cache-line aligned CPU state, Performance Tuning CacheLineGranularity CacheLineMatch CacheManipulation CacheMiss CacheParameter CacheRegister CacheReplacementPolicy CacheTiming Calculation California CALL_CENTRY_BEG CALL_CENTRY_END CALL_KERNEL_BEG CALL_KERNEL_END CALL_PAL CALL_PAL_BEG CALL_PAL_END CALL_PAL_INSTRUCTION Callback Caller CallPal CALLSYS candidate canDualIssue CanonicalAddress Canonicality CanonicalPARoutingTable CanonicalPTE CanonicalType Capability Capacity Carry CBox Cbox-CSR CBoxLib CBoxState CC CC_CTL C-data CentralizedInvalidation CFLUSH Chapter Chapter 11 – Architectural Invariants Chapter 12 – AlphaCPU Core Chapter7_ExceptionsFaultsAndInterrupts Check checkBarrierRelease checkInterrupts checkReservation checksum ChipID Chipset CHME CHMK CHMS CHMU CIX ClaimedInterrupt claimNext Clang classes Classification cleanPC Cleanup clear ClearAllReservations clearArithmeticTrap clearDirty clearIPRStaging clearMissStaging clearPendingEvents ClearReservation Clipper clock algorithm clock hand ClockCycle ClockDomain ClockedExecution ClockPolicy CLR_MAP CM CM_KERNEL CMake CMField cmov CMOVEQ CMOVGE CMOVGT CMOVLE CMOVLT CMOVNE CMPBGE CMPEQ cmpEqL cmpEqQ CMPLE cmpLeL cmpLeQ CMPLT cmpLtL cmpLtQ CMPSEQ CMPSLE CMPSLT CMPSUN CMPTEQ CMPTLE CMPTLT CMPTUN CMPULE CMPULT CMType CodeGeneration CodeLayout CodeVolume Coherence Coherency Coherency isolation CoherencyCoordination ColdIPR ColdPartition ColdPath cold-path Command Comment Commit commitInstruction commitPalResult commitPending CommitPoint commitPrevious CommitStage Communication Comparison Comparison-Legacy CompilerDetection CompileTime Completion CompletionFlag CompletionRequirement CompletionSignal Complexity Component boundaries Component contracts COMPONENT_NAME Computation computeCallPalEntry ComputedVector computeExceptionVector Concern Concurrency ConcurrencyModel Condition Conditional ConditionalLogging ConditionalMove ConditionCode ConditionEvaluation config configLib Configuration ConfigurationSpace Conflict ConflictWrite ConservativeSpeculation Consistency console ConsoleControl ConsoleOutput ConsoleService Constant Constexpr Constraint Constraints constructor injection Constructor pattern Context ContextBlock ContextFrame ContextRestore ContextRevert ContextSave ContextSeparation ContextSlot ContextSnapshot ContextSwitch context-switch ContextSwitchPrimitive ContiguousMemory Continuation Contract control Control flow ControlFlow ControlledInterface Controller Controllers ControlLogic ControlMode ControlRegister ControlTransfer Conversion Conversion-Legacy ConveyorBelt Coordination CoordinationEvent copyExitOff copyLoop copyLoopMs copyLoopOff copyLoopSteps CopyOnWrite Core Interrupt Flow CoreArithmeticHelpers CoreLib COROUTINE Corrected Correctness Correctness over speed CorrectnessGuarantee Count Counter countTrailingZeros64 Coupling Coverage COW CPlusPlus20 CPlusPlusImplementation CPU CPU affinity routing, Device Interrupt Integration CPU IPL (Interrupt Priority Level) CPU IRQ State CPU run loop integration, CPU Integration CPU_EV CPU_ID_INVALID cpu_trace.log cpu_trace.lst CPUContext CPUContextBinding CPUCoordination cpuCoreLib cpuCoreLib/AlphaPipeline.h cpuError CPUFamily cpuHalted CPUId CPUIdentifier CPUIdentity CPUIdType CPUInstance CPUInstantiation CPUInterruptState CPUIpl CPUIRQState CPUIsolation cpuList CPUNotification CPUOwnership CPUReservation CPUState CPUStateIPRInterface CPUStateIPRInterface CTOR CPUStateIPRInterface per-CPU instantiation CPUStateIPRInterface SPAMShardManager pointer CPUStateIPRInterface SPAMShardManager reference CPUStateManager CPUStateManager_h CPUStateView CPUtoIRQBoundary cpuTrace CPUWorker CPUWorkerStruct createWorkers Critical CriticalPath CrossBoundaryViolation CrossCPU Cross-CPU synchronization CrossCPUCommunication CrossCPUCoordination CrossCPUEvent CSERVE C-shift CSR CTLZ CTPOP CTTZ ctz CurrentASN CurrentCpuTLS CurrentMode custom invalidation policy custom replacement policy custom routing policies, Advanced Topics CustomPlatform CVTFQ CVTQF CVTQS CVTQT CVTST CVTTQ CVTTS cycle CycleAccounting Cycle-based emulator Cycle-based execution Cycle-based run loop CycleBasedExecution CycleCount CycleCounter cycle-counter CycleDriven CycleExecutionModel CycleGranularity CycleIncrement CycleInvariant CycleIteration CycleMechanics CyclePhase cyclesExecuted CycleTiming Data Data Alignment Trap Data flow DataAccess DataForwarding DataRealm DataStructure DataTLB DataTranslation DataTranslationBuffer DATFX DC_CTL DC_STAT D-cache DE Debug Debuggability Debuggable execution Debugger DebuggerHook DebuggerIntegration Debugging Debugging & Diagnostics DebugReplay DebugService DebugSummary DEC DEC Alpha fidelity DEC Alpha hardware Decision Decode DecodeCache DecodedInstruction decodePCTX_ASN decodePCTX_ASTER decodePCTX_ASTRR decodePCTX_FPE decodePCTX_PPCE DecoderTable DecodeStage decodeVAFromTag decompress decompressor decOut Default DefaultInvalidationStrategy Deferred DeferredDelivery DeferredFault DeferredWriteback deferWriteback Delegation DelegationModel DeliverableInterrupt deliverException deliverInterrupt Delivery DeliveryCompletion DeliveryCondition DeliveryOrdering DeliveryPrecision DeliverySemantics DeliverySequence DemandPaging Dependency descriptor Design DesignChoice DesignPhilosophy DEStage Detection Determinism deterministic Deterministic execution Deterministic replay DeterministicBehavior DeterministicExecution DeterministicOrdering Developer orientation Device Device Integration device interrupt registration, Device Interrupt Integration Device IRQ Device IRQ Vector Device isolation device ISR dispatch, Device Interrupt Integration Device models DeviceAddressSpace DeviceCompletion DeviceCSR DeviceDriver DeviceEmulator DeviceEndianness DeviceIntegration DeviceInterrupt deviceInterruptVector deviceLib DeviceOperation DeviceRouting Devices DeviceSource DeviceState DeviceTemplate DevSpace Architecture (Ch.1–11) DevSpace Implementation (Ch.12–22) DFAULT DFAULT_ACV DFAULT_FOE DFAULT_FOR DFAULT_FOW DFloat di Diagnostics DirectInvocation DirectVector Discard DiscreteTime Dispatch DispatchAddress Dispatcher DispatchMechanism DispatchStub DispatchTable Displacement DisplacementBased Distinction Divide DivideByZero Division DivisionByZero DIVL DIVLV DIVQ DIVQV DIVS DIVT DMA DMACoherencyManager DMAWrite documentation domain Domain isolation Domains donePC DoublePrecision Drain DRAINA DrainCondition Draining drainWriteBuffers DS10 DS10_V6_2.exe DS20 DS20_V6_2.exe DS20L_V6_2.exe DStream DStreamFaultType DTB DTB_ALTMODE DTB_ASN0 DTB_IS0 DTB_IS1 DTB_MISS DTB_MISS_DOUBLE_3 DTB_MISS_DOUBLE_4 Dtb_miss_native DTB_MISS_SINGLE DTB_PTE_FAULT DTB_PTE_NATIVE DTB_PTE0 DTB_PTE1 DTB_TAG0 DTB_TAG1 DtbAcv DTB-ASN DTBInvalidation DTBM_DOUBLE DTBM_SINGLE DTBManagerType DtbMiss DTBMissDouble DTBMissNative DTBMissSingle DTB-pte DTB-tag DTBVictimPolicy DualAxis DualCache DualDTB DualDTBManagerInterface DualDTBManagerInterface.h DualIssue Duplication EarlyReturn EBox EBoxLib EBoxVAState ECB edge-triggered interrupt, Device Interrupt Integration EffectiveAddress elapsedMs elapsedTime ElevatedIPL ElevatedPrivilege Emulated Interrupt Emulator emulatorBuildId EmulatorConfiguration EmulatorManager EmulatorSettings EmulatorSubsystem EMulatR EmulatR_init EmulatR_init.cpp EmulatR_init_cpp EmulatRAppUni emulatrLib Enable Encapsulation encodePCTX Encoding Endianness EndPA Enforcement Enqueue enterPal enterPalCore enterPalMode Entry entry invalidation EntryAddress EntryBarrier EntryIPL EntryMapping EntryMetadata EntryPC EntryPoint EntryReason EntryStride EntryTransfer EntryVector Enumeration Environment EnvironmentVariable envysys_com eNVySystems Epoch Equality EQV Error ERROR_LOG ES40 ES40_V6_2.exe ES45 ES45_V6_2.exe ESP EV4 EV5 EV6 EV6 (21264) EV6 (21264) target Ev6_DtbPteTraits EV67 EV68 EV6Silicon Ev6SiliconTLB Ev6Translator Evaluation event EventBit EventBitmask eventClass EventClassification EventClearance EventClearing EventDeferral EventDelivery EventDispatch EventEvaluation EventHandling EventInjection EventIntegrity EventIsolation EventLifecycle EventMask EventOrdering EventOrigin EventPending EventPreservation EventPriority EventQueue EventRouting EventSampling EventSource EventState EventVector Eviction EVT EX EXC_ADDR exc_Mask EXC_SUM exc-addr EXCB EXCB barrier exception Exception semantics Exception Vector Map ExceptionAccounting ExceptionAddress ExceptionalEvent ExceptionBarrier ExceptionBoundary exceptionClass ExceptionClass_EV6 ExceptionClassification ExceptionContext ExceptionDelivery ExceptionDispatch ExceptionEnforcement ExceptionEntry ExceptionFactory ExceptionFactory_inl ExceptionFactory_inl.h ExceptionFrame ExceptionHandler ExceptionHandling ExceptionInteraction exceptionLib ExceptionMapping ExceptionMapping_inl ExceptionMasking ExceptionModel ExceptionOffset ExceptionOrdering ExceptionPrecision ExceptionPreparation_inl ExceptionPriority ExceptionRegister ExceptionReturn ExceptionSafety ExceptionSemantics ExceptionState ExceptionStateUpdate_inl ExceptionStatus ExceptionSummary ExceptionVector exc-mask exc-sum ExecTrace EXECTRACE_PIPELINE_FLUSH EXECTRACE_WB_RETIRE ExecUnit execute ExecuteDisable executeEXCB executeMB ExecuteMethod ExecutePermission executeREI ExecuteStage executeTRAPB executeWMB execution Execution interaction Execution isolation Execution model Execution model definition ExecutionAdvance ExecutionBlock ExecutionBoundary ExecutionBox executionBoxDecoder ExecutionContext ExecutionCoordinator ExecutionCoordinator_h ExecutionDelegation ExecutionDependency ExecutionDispatch ExecutionEngine ExecutionFlow ExecutionFlush ExecutionIsolation ExecutionLatency ExecutionLoop ExecutionMode ExecutionOrder ExecutionOrdering ExecutionPhase ExecutionPolicy ExecutionProgress ExecutionRestart ExecutionRestriction ExecutionStage ExecutionState ExecutionTimeCheck ExecutionTrace ExecutionUnit Executive Stack Pointer ExecutiveMode executive-stack ExitBarrier exitPalMode Expansion Explicit barrier coordination Explicit serialization ExplicitIdentity ExplicitOrdering ExplicitSerialization EXStage EXT EXTBL EXTLH EXTLL EXTQH EXTQL extract extractField extractFunction extractOpcode extractRA extractRB extractRC EXTWH EXTWL Failure Fallback FastPath Fatal Fault Fault dispatch fault sink integration, CPU Integration FAULT_ACV FAULT_ARITH FAULT_DTBM FAULT_ITB FAULT_UNALIGNED FaultBit FaultClassification FaultContainment FaultDeferral FaultDelivery FaultDetection FaultDispatch faultDispatched FaultDispatcher FaultDispatcher_h FaultHandling FaultingInstruction FaultingPC FaultMasking FaultOnExecute FaultOnRead FaultOnWrite faultPC faultPending FaultQueue FaultRecording FaultReporting FaultSemantics FaultState FaultType faultVA FaultVector FBEQ FBGE FBGT FBLE FBLT FBNE FBox FBoxLib FCMOVEQ FCMOVGE FCMOVGT FCMOVLE FCMOVLT FCMOVNE FEN Fence Fetch FETCH_M fetchAndDecode FetchBlock fetchNext FetchPC FetchRestart FetchResult FetchStage FFloat Fidelity Field FieldSelect FIFO Figure finalPalBase finalPC find fine-grained sharding Firmware FirmwareBlob FirmwareImage FIXED_CPU routing, Device Interrupt Integration Flag FLAG_ARITHMETIC_TRAP FLAG_DTB_MISS FLAG_EXCEPTION FLAG_INTERRUPT FLAG_ITB_MISS FLAG_MACHINE_CHECK FLAG_NONE flags FloatingOverflow FloatingPoint floating-point Floating-Point Enable Floating-Point Exception FloatingPointControlRegister FloatingPointDisabled FloatingPointEnable FloatingPointException FloatingPointExecution FloatingPointOperation FloatingPointOps FloatingPointRegister FloatingPointRegisterFile Flow flush FLUSH_EVERY FlushEvent Flushing FlushMechanism flushPipeline FlushPolicy flushPredictionState FlushRequest FlushTrigger flushYoungerSlots Flyweight FNV FNV-1a FOE FOR Format Forward Forwarding ForwardingMechanism ForwardingPath ForwardProgress FOW FP32 FP64 fpClearDirty FPCR FPCRType FPE fpReg FPRegisterFile fpValid fpValue FPVariant Frame Freeze fromDtbPteWrite fromItbPteWrite fromSnapshot Frontend FrontendBlock FrontendInvalidation FrontendStall FullBarrier FullFlush FullPath FullSerialization Function Functional Boxes FunctionalDomain functionCode FunctionField FunctionRange FunctionSelector FutureExpansion fuzzing GateLevel GCC General GeneralPurposeRegister generate_all_grains generate_all_grains.py GENTRAP getActiveCPUCount getActiveSP getAsm getFpRegs GetFpRegsFn GetIntRegsFn GetIprsFn getPredictedTarget getTraceMask GFloat GH ghCoverage GitHub github_com Global Global IRQ Controller global_EmulatorSettings global_EmulatR_init global_GuestMemory Global_HWPCBBank_Interface.h global_IPIManager Global_IPLBank_Interface.h Global_IRQController.h/CPP global_MemoryBarrierCoordinator Global_PALVectorTable.h GlobalBarrier GlobalCoordination globalDMACoherencyManager globalDtbManager globalEpoch globalFaultDispatcher GlobalFlag globalGenAtFill GlobalHistory GlobalHWPCBBank GlobalHWPCBController globalInstructionGrainFactory globalIPICoordinator globalIPR globalIPRCold globalIPRHot globalIPRIbox GlobalIPRInterface globalIprRegistry globalIRQController globalItbManager GlobalOrdering globalPalVectorTable globalReservationManager GlobalSubsystem GlobalSynchronization GlobalVisibility Grain GrainAutoRegistrar GrainDispatch GrainFactoryLib GrainMaster GrainMaster.tsv GrainPlatform GrainRegistrationCore GrainResolver Grains GrainType Granularity GranularityHint GS160 GS320 GS320_V62.exe GS80 Gshare Guarantee GuestMemory GuestPhysicalRegion GuestPhysicalRegionRegistry GuestRegionSource GuestRegionType HALT HaltCondition HALTED HaltedCPU HaltedState HaltRequest handleFPTrap handleInterrupt Handler HandlerDispatch handleRead HandlerEntry HandlerMethod handleTLBShootdownIPI handleWrite Hardware Hardware Interrupt HardwareAbstraction HardwareBehavior HardwareClock HardwareCycle HardwareInterface HardwareInterrupt HardwareIRQ HardwareMode HardwareOffset HardwarePrivilegedContextBlock HardwareRegister HardwareRestartParameterBlock HardwareReturnFromException HardwareSoftwareBoundary HardwareSoftwareInterface HardwareSpeculation HardwareVector HardwareWriteEnable hasDeliverable Hash hash bucket hasPendingArithmeticTraps hasPendingInterrupt hasPendingMachineCheck hasPendingTLBFaults Hazard HazardCheck HazardDetection HazardResolution Header HeaderFile headerSkip HeadPointer Helper helpers Here is a **vertical noun-only k-keyword list** for your topic (Alpha exceptional event classification model): Here is your **vertical noun-only k-keyword list** for Exception, Serialization, and Reservation interaction: Here is your **vertical noun-only k-keyword list** for Section 8.4 (CALL_PAL, serialization, entry mechanics, and PalEntryReason): Here is your **vertical noun-only k-keyword list** for Section 8.5 (PAL entry vector computation model): Here is your **vertical noun-only k-keyword list** for Section 8.6 (PAL execution context and privilege lifting): Here is your **vertical noun-only k-keyword list** for sections 2.2.1 and 2.2.2: Here is your **vertical noun-only k-keyword list** for Sections 2.5.1–2.5.3 (Forward Progress and Stalls): Here is your **vertical noun-only k-keyword list** for Sections 2.7.1–2.7.2 (Execute and Writeback semantics): Here is your **vertical noun-only k-keyword list** for the AlphaCPU run loop architecture: Here is your **vertical noun-only k-keyword list** for the Arithmetic Trap and TRAPB interaction model: Here is your **vertical noun-only k-keyword list** for the cycle phase architecture (Section 2.4): Here is your **vertical noun-only k-keyword list** for the speculation and flush model: Heuristic Heuristics Hierarchical navigation Hierarchical structure highestPendingLevel HighPosition Hint HistoryTable Hit HitRate HostNativeFormat HostOptimizations HostOrdering HostThreadContext hot path optimization, Performance Tuning HotIPR HotPartition HotPath hot-path HotPathLogging Housekeeping HW_INT_CLR HW_LD HW_MFPR HW_MTPR HW_REI HW_REI return path, PAL Integration HW_RET HW_ST HWE HWINT hwIPL HWPCB HWPCB_core HWPCB_core.h HWPCBBank HWPCBSlot HWRPB hwVector I_CTL I_STAT IACV IBox IBoxBase IBoxIPR IBoxLib IC_FLUSH IC_FLUSH_ASM ICache I-cache ICacheFlush ICCSR ICEnable ICFlush ICtl ICtlRegister Identifier IdentifierAssignment Identity IDeviceEmulator IEEE IEEE754 IEEEIdentity IER IER_CM IF IFAULT IFStage ILLEGAL_INSTRUCTION IllegalInstruction IllegalJump IllegalOpcode IllegalReturn IMB immediate immediateDecode Implementation Implementation chapters (12–22) Implementation separation ImplementationStrategy ImplicitOrdering ImplicitSequencing ImplicitSerialization ImplicitState IMPLVER includeInSnapshot IndependentExecution IndependentRunLoop Index Indexed IRQ Indirect Inexact InFlight INFO_LOG INFRASTRUCTURE INIParser Initialization InitializationCoordinator InitializationPattern initialize initializeDeviceInterrupts initializeSystem initiatingCpu initLib initSteps Injection Inlining InOrder inPalMode Input INS INSBL insert insertDTB insertField insertITB inServiceMask INSLH INSLL Inspectable state INSQH INSQL Instance Instruction Instruction decode isolation InstructionAdvance InstructionAdvancement InstructionAssociation InstructionBlock InstructionBoundary InstructionBox InstructionCache InstructionCommit InstructionCompletion InstructionControl InstructionDecode InstructionDiscard InstructionEncoding InstructionEnforcement InstructionExecution InstructionExtensions InstructionFault InstructionFetch InstructionFormat InstructionGrain InstructionGrainFactory InstructionGrainRegistry InstructionGrains InstructionIssue InstructionOrdering InstructionRealm InstructionRetirement InstructionSemantics InstructionSet InstructionSlot InstructionStream InstructionTLB InstructionTranslationBuffer InstructionWord Instrumentation INSWH INSWL intClearDirty Integer IntegerArithmetic IntegerConversion IntegerLogic IntegerOperate IntegerOverflow IntegerRegister IntegerRegisterFile Intentionality Interaction Interface InterfaceBoundary InternalError InternalProcessorError InternalProcessorRegister inter-processor interrupt (IPI), IPI Integration InterProcessorInterrupt InterProcessorSignal interrupt Interrupt Acknowledge interrupt acknowledgement, Device Interrupt Integration interrupt affinity optimization, Advanced Topics interrupt coalescing, Advanced Topics interrupt controller, Overview Interrupt Delivery interrupt delivery, Architecture interrupt dispatch, Architecture interrupt eligibility report, Debugging and Diagnostics interrupt eligibility, Debugging and Diagnostics interrupt fairness, Performance Tuning interrupt fast path, Performance Tuning interrupt latency reduction, Performance Tuning Interrupt Masking interrupt masking, Architecture Interrupt Pending Interrupt Posting Interrupt Priority interrupt priority level (IPL), Architecture Interrupt Queue interrupt queue sharding, Architecture Interrupt Register Interrupt Reset interrupt routing policy, Architecture Interrupt Service Routine (ISR) interrupt state dump, Debugging and Diagnostics interrupt statistics counters, Debugging and Diagnostics interrupt trace logging, Debugging and Diagnostics Interrupt Vector interrupt vector, Architecture InterruptAcknowledge InterruptArbitration InterruptCheck InterruptClassification InterruptControl InterruptController InterruptDelivery InterruptDispatch InterruptEligibility InterruptEnable InterruptHandler InterruptHandling InterruptMask InterruptMasking InterruptPending InterruptPriority InterruptPriorityLevel InterruptRouter InterruptSampling InterruptSemantics InterruptState InterruptTracking InterruptVector InterruptVectorOffset IntraCycle intReg intValid intValue Invalidate invalidate entry invalidate method invalidateAllDTB invalidateAllITB invalidateAllTLBs invalidateASN invalidateNonASM InvalidateRange invalidateTLBsByASN Invalidation invalidation strategy InvalidationPolicy InvalidOperation Invariant Invocation IOBridge IOController IPBit IPI IPI (Inter-Processor Interrupts) IPI delivery IPI dequeue processing, CPU Integration IPI queue handling, IPI Integration IPI_core IPI-based invalidation IPICoordination IPICoordinator IPIInterrupt IPIManager IPIMessage IPIRouting IPIs IPL IPLArbitration IPLCanonical IPR IPR (Internal Processor Register) IPRAccess IPRBank IPRIndex IPRInteraction IPRManipulation IprPair IPRRead IPRRegion IPRRegistry IPRs IPRStaging IPRStorage IPRStorage_Cold IPRStorage_core.h IPRStorage_Hot IPRStorage-Cold IPRStorage-Hot IPRStorage-IBox IPRValue IPRWrite IRQ IRQ (Interrupt Request) IRQ Bank IRQ Controller IRQ Handler IRQ Mask IRQ Priority IRQ Vector Table IRQController IRQPendingState IrqTemplate Irreversible IS ISA ISAExtensions isAlive isBranchFormat isCPUHalted isFrontendStalled isGlobal isInPalMode isLoaded isMemoryException isMemoryFormat isNegL isNegQ Isolation isOperateFormat isPipelineStalled ISStage Issue issueMemoryBarrier IssueStage isSynchronousException ISUM isValid isZeroL isZeroQ ITB ITB_IA ITB_IAP ITB_IS ITB_MISS ITB_PTE ITB_PTE_FAULT ITB_TAG ITBAccessViolation ItbAcv ITB-ASN ITBInvalidation ITBManagerType ITBMiss ITB-pte ITB-tag ITBVictimPolicy ITMISS IVA_FORM JIT JMP JSR JSR_COROUTINE jsrOffset Jump kCopyExitPC kCopyLoopPC kDecompSig Kernel Kernel Stack Pointer KernelMode KernelPrivilege KernelReadEnable kernel-stack KernelWriteEnable kHalt kind kJsrScanLimit kJsrToFinalPC kLdaMask kLdaPattern kRealmCount (static) kResetEntry KSEG kSizeClassCount (static) kSnapshotMagic kSnapshotVersion KSP L1 L2 L3 Latency LatencyModeling Layer LayeredSeparation Layers Layout Lazy LazyDecode LazyInitialization LDA LDAH LDBU LDF LDG LDL LDL_L LDQ LDQ_L LDQ_U LDS LDT LDWU LDx_L Least Recently Used (LRU) Legacy LessOrEqual LessThan LetterBox Level LevelBits level-triggered interrupt, Device Interrupt Integration LFU License Lifecycle LifecycleManagement Likely Line lineCounter Linux Linux_Alpha listing LiteralLogging LittleEndian LL LL_SC LL_SCInteraction LL_SCReservation LLSC Load LoadCompletion LoadExecution loadFromFile LoadInstruction LoadLinked LOADLOAD LoadLocked LoadOperation loadPA LoadPattern loadSnapshot LocalBuffer LocalDrain Lock LockFree lock-free hot path, Key Design Principles lock-free polling, Key Design Principles lock-free sharding log Logging LoggingMacros Logical logicalAnd LogicalIndex logicalNand logicalNor LogicalOperation logicalOr logicalXor logs Longword lookup lookupDTB lookupITB Loop LowBitIndicator LowBits LOWEST_IPL routing, Advanced Topics LowLevelCoordination LowMemory LowPosition LRU m_cBox m_cboxes m_cpuCount m_cpuStateManager M_CTL m_cycleCount m_eBox m_fBox m_head m_instructionsRetired m_mBox m_nextSequence m_occ m_palBox m_pending m_pendingFetch m_reservationManager m_shards m_slots m_totalCycles m_ver m_workers MACHINE_CHECK MachineCheck machine-check MachineCheckReason machineOut main_cpp MainEntryPoint MainRAM Maintainability Maintainer guidance maintenanceTick Major subsystems makeArithmeticEvent makeBreakpointEvent makeBugcheckEvent makeCallPalEvent makeDTBAccessViolationEvent makeDTBFaultEvent makeDTBMissDouble3Event makeDTBMissDouble4Event makeDTBMissSingleEvent makeFENEvent makeGrainKey makeIllegalOpcodeEvent makeInterruptEvent makeITBAccessViolationEvent makeITBMissEvent makeMachineCheckEvent makeMTFPCREvent makeResetEvent makeSoftwareTrapEvent makeTag makeUnalignedEvent Management manager Manager pattern manual Map mapClassToPalVector Mapping mapTrapToPalVector Mask Masking MAX_CPUS MaxASN Maximum maxSteps MB MB barrier MB2 MBInstruction MBox MBoxLib_EV6 MCES MCHK mchkAddr mchkCode Meaning Mechanism MEM MEM_STATUS Memory Memory isolation Memory ordering Memory ordering rules Memory subsystem MemoryAccess MemoryAccessStrategy MemoryArchitecture MemoryBackedCode MemoryBarrier memoryBarrierCompleted MemoryBarrierCoordinator MemoryBarrierKind MemoryBarrierKind_PAL MemoryCommit MemoryConsumption MemoryDrain MemoryEffect MemoryFault MemoryImplementation MemoryIO MemoryLayout memoryLib MemoryLoad MemoryMap MemoryMappedIO MemoryModel MemoryOperation MemoryOrdering MemoryPath MemoryProtection MemoryRegion MemorySize MemorySpan MemoryStage MemorySubsystem MemorySynchronization MemorySystem MemoryTranslation MemoryView MemoryWrite MEMStage Metadata Method MeyersSingleton MF_FPCR MFPR MFPR_ASN MFPR_ASTEN MFPR_ASTSR MFPR_CC MFPR_DTB MFPR_ESP MFPR_FEN MFPR_IER MFPR_IPL MFPR_ISR MFPR_KSP MFPR_MCES MFPR_PCBB MFPR_PRBR MFPR_PTBR MFPR_SCBB MFPR_SISR MFPR_SSP MFPR_SYSPTBR MFPR_TBCHK MFPR_USP MFPR_VPTB MFPR_WHAMI Microarchitecture Microcode milestone mini-cache Minimum mirrorPA Misprediction Miss MissDetection MissStaging MM_STAT mmAccessType mmFaultReason MMIO mmio_DMACoherencyManager mmio_Manager MMIOIndicator mmioLib MMIOManager MMIORegion MMIORouting MMU MMU (Memory Management Unit) MMUInvalidation mnemonic Mode ModeBit ModeCheck ModeDependentState ModeEncoding Model ModeTransition Modularity Modulo Monolith MRU MSK MSKBL MSKLH MSKLL MSKQH MSKQL MSKWH MSKWL MSVC MT_FPCR MTPR MTPR_ASN MTPR_ASTEN MTPR_ASTSR MTPR_CC MTPR_DTB MTPR_ESP MTPR_FEN MTPR_IER MTPR_IPL MTPR_ISR MTPR_KSP MTPR_MCES MTPR_PCBB MTPR_PRBR MTPR_PTBR MTPR_SCBB MTPR_SIRR, Software Interrupts MTPR_SISR MTPR_SSP MTPR_SYSPTBR MTPR_TBCHK MTPR_USP MTPR_VPTB MTPR_WHAMI Mul64 MULL MULLV MULL-V mulQ MULQV MULS MULT multicore sharding MultiCPU Multi-CPU Interrupts MultiCycle Multiplication Multiply Multiprocessor correctness mustComplete mutex MVI MyDTBTraits MyITBTraits NaN NAND NativeImplementation needsMemoryBarrier needsWriteback needsWriteBufferDrain Negative NestedException NeverInline NeverTaken nextPC No cross-domain state access No implicit ordering NoDiscard NoMasterCPU NON_DETERMINISTIC NonCanonical NonCanonicalAddress NonFPCR NonGoals Non-goals reference NonHaltedCPU NonOverlappingRegion NonPalMode NOR NormalPipeline Normative chapter Normative specification NoSideEffects Notification Observability Observation Occupancy Offset OffsetAddition OffsetBase OffsetMask OffsetShift OldestInstruction OnDemandAllocation One cycle per iteration OneInOneOut One-way dependency flow onIPLChanged OPCDEC OpcDecFault Opcode OpcodeExtraction OpcodeField OpenVMS Operand operands Operate OperatingSystem OperatingSystemInterface Operation operations OptimisticReservation Optimization Optimization constraints Optimization safety OptimizationHints Option OptionA OptionB OptionC OptionD OR Ordering OrderingBoundary OrderingEnforcement OrderingGuarantee OrderingStrength OrderOfOperations ORNOR ORNOT OSF_1 OSReflection Outcome OutOfOrder output Overflow OverflowDetection Overhead Ownership ownership hierarchy PA PACache PaDecodeCache Page Page Table Base Register PAGE_SHIFT PAGE_SIZE PageAlignment PageAllocation PageAllocator PageBoundary PageDirectoryEntry PageDuplication PageFrameNumber PageGeometry PageIndex PageMask PageNotPresent PageShift PageSize PageSizeCode (enum) PageSizeHelpers (class) PageTable PageTableEntry PageTableWalker PageWalk PaKey PAL PAL entry on interrupt, PAL Integration PAL entry serialization PAL interrupt blocking, PAL Integration PAL interrupt entry, PAL Integration PAL mode awareness, Architecture PAL Scratch Area PAL Semantics PAL_BASE PAL_CALL PAL_core PAL_core.h PAL_core_inl PAL_SCRATCH[8] PALBarrier palBase PAL-base PalBoundary PalBox PalBoxBase PalBoxBase_h PalBoxLib PalCall PalCallInstruction PALCallsChapter PALcode PALContext PalDispatch PAL-end PalEntry PalEntryPoint PalEntryReason PalEntryReasonEnum PalEntryVector PalExecution PalExit palFunction PalFunctionSelector PalHandler palLib_EV6 PALmode PalModeFlag PalModeIndicator PalOperation PALReservationClear PalResult PalSelector PalSerialization PalService PALStyle PALtemp PALTransition palVector PalVectorComputation PalVectorId PalVectorId_EV6 PalVectorId_EV6_h PalVectorSelection PalVectorTable Panic parallel cache ParallelExecution PARange PARouteEntry PARouting parser PartialFlush participatingCpus partitioned cache partitioned data structure Partitioning paToSafeMemoryOffset PAType pauseCPU PauseOperation payLoad payloadSize PC PCBB PCBit0 PCCache PcDecodeCache PCI PCIConfigurationSpace PcKey pcReason PCTR_CTL PCTX pctx_hw_mtpr_write PCUpdate PDE PeerArchitecture PeerCPU Penalty PendingCommit PendingEvent PendingEventKind PendingException PendingInterrupt PendingInterrupts pendingLevelsMask PendingPropertyInfo pendingSourcesByLevel PendingTrap per-bucket state PerCPU per-CPU per-CPU interrupt queue, Architecture Per-CPU Interrupt State per-CPU interrupt state, Architecture per-CPU invalidation per-CPU IPL tracking, CPU Integration per-CPU shard per-CPU shard, Architecture per-CPU TLB per-CPU TLB invalidation, IPI Integration per-CPU TLB slice PerCPUEpochTable PerCPUIsolation PerCPUReservation PerCPUState PerDeviceConfiguration per-entry state PERFMON Performance & Hot Path Performance secondary PerformanceBalance PerformanceCounter performance-counter PerformanceCounterEnable PerformanceHints PerformanceMonitor PerformanceOptimization Permission PermissionBit PermissionMask Permissions permMask PermMask (static) per-realm shard per-size-class shard PerThreadState pfn PFN (Page Frame Number) PFN_SHIFT PFN_WIDTH PFNType PhaseOrdering PhaseOverlap PhaseSequence PhysicalAddress PhysicalAddressRouter PhysicalAddressSpace PhysicalFrame PhysicalMemory PhysicalMemoryAccess PhysicalRAM PIP pipeline Pipeline contract pipeline flush on interrupt, CPU Integration Pipeline mechanics PipelineAction PipelineAdvance PipelineAdvancement PipelineBookkeeping PipelineBoundary pipelineDelay PipelineEffect PipelineEnforcement PipelineExecution PipelineFlush PipelineIsolation PipelineOccupancy PipelineOrdering PipelineOwnership PipelinePhase PipelineQuery PipelineRedirect PipelineReset PipelineSerialization PipelineSlot PipeLineSlot.h PipelineStage PipelineStall PipelineState PipelineStepResult PipelineSummary PipelineTick PipelineWideBlock PipelineWideSerialization platform Platform arthitecture PlatformCapabilities PlatformConfig PlatformDetection PlatformPolicy Platforms Pointer policy code sample policy design decision policy extensibility policy implementation policy interface policy limitations policy state policy template parameter policy usage PolicyEvaluation Polymorphic populateDescriptor Portability Position Post Interrupt postCopySteps PPCE PRBR Precise Precise exceptions precise interrupt delivery, PAL Integration PreciseDelivery PreciseException PreciseExceptionModel PreciseOrdering PreciseSemantics PreciseState PreciseTrap Precision PreCycleCheck predictedTarget prediction predictionTarget PredictionUpdate predictionValid predictTaken predTaken predTarget Preemption PreExceptionState Prefetch Preparation prepareAndDeliverException preparePendingEventForDelivery Primary design goals Primitive Priority PriorityCondition PriorityLevel PrivateState Privilege Privilege boundaries Privilege isolation PrivilegeArbitration PrivilegeBit PrivilegeBoundary PrivilegeCheck PrivilegedAccess PrivilegedArchitectureLibrary PrivilegedBoundary PrivilegedCallPal PrivilegedContext PrivilegedExecution PrivilegedFunction PrivilegedInstruction PrivilegedMode PrivilegeDomain PrivilegedOpcode PrivilegedOpcodeFault PrivilegedOperation PrivilegedRange PrivilegedRegister PrivilegedSerialization PrivilegeElevation PrivilegeEnforcement PrivilegeEscalation PrivilegeHierarchy PrivilegeIsolation PrivilegeLeak PrivilegeLeakage PrivilegeLevel PrivilegeMode PrivilegeSeparation PrivilegeSerialization PrivilegeState PrivilegeTransition PrivilegeViolation probe Process Process Region Base Register ProcessContextRegister Processor ProcessorMode ProcessorState ProcessorStatus processor-status ProcessorType ProgramCounter ProgramCounterUpdate ProgramOrder progress ProgressFn ProgressGuarantee project Prompt Propagation Property ProtectionHelpers (class) Protocol PS PSRegister PTBR PTE PTE Subsystem PTECache pteLib PTETraits PTETraits<CPUFamily> PTEType PTEView PTW Publish PureFunction Purpose Python Q_EMULATR_RANDOM_INT Q_GLOBAL_STATIC QDataStream QDebug QElapsedTimer QFile QMutex qrand QRandomGenerator QScopedPointer QSettings QStringLogging Qt QT_COMPAT QtBitUtilities QtEventLoop QTextStream QThread QtRandom QtSignal Quadrant Quadword QuadwordReservation Qualifier Query queryPrediction Queue QuiescedState QVarLengthArray R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 RaceFreedom raiseOpcodeFault raiseTrap RAM RANDOM random victim policy RANDOMNESS RandomPolicy Range RAS RAW rawBits rawInstr RC RD_PS RDMCES Read READ_UNQ read64 ReadAPI ReadBarrier ReadCompletion ReadOnlyMasking ReadOnlyRegion ReadPermission ReadPhysicalFn ReadQueue Realm Realm (enum) Recommendation recordAccess recordBranchResolution recordPrediction Recovery Redirect Refactor constraints Refactor safety Reference reference bit Refill REG Region Register Register IRQ Vector REGISTER_GRAIN RegisterAccessPattern RegisterContext registerDeltas RegisterDependency RegisterFile RegisterIsolation RegisterMatrix RegisterRead RegisterScoreboard RegisterSnapshot RegisterUpdate RegisterUsage RegisterVisibility RegisterWrite Registration Registry REI Release ReleaseCondition ReleaseLogic ReleasePattern RendezvousFailure Reordering Replacement replacement policy ReplacementPolicy replacement-policy ReplacementPolicyBase ReplacementPolicyEnum REPLAY_SENSITIVE Reproducibility Reproducible behavior RequestMemoryBarrier requiresCallPalCalculation re-reference prediction value Reservation Reservation tracking ReservationAlignment ReservationCallback ReservationClearing ReservationGranularity ReservationInteraction ReservationInvalidation ReservationManagement ReservationManager ReservationModel Reservations ReservationSlot ReservationState ReservationStats ReservationTimestamp ReservationTracking ReservedOperand ReservedRegion RESET ResetOperation resetPalMode ResetState Resolution resolveGrain ResourceIsolation ResourceOccupation Responsibility RESTART restoreContext result resultL ResultNormalization resultQ resumeCPU Resumption RET Retire Retirement RetirementBoundary RetirementFault RetirementMechanics RetirementOrdering RetirementPoint RetirementUpdate Retry RETSYS ReturnAddressStack ReturnInstruction ReturnPath ReturnPC ReverseOrder Reviewer guidance RingBuffer RingRotation RISC Rollback ROM romHash Rotation ROUND_ROBIN routing, Device Interrupt Integration Rounding Rounding-Legacy RoundingMode Router RouteTarget Routing routing affinity hints, Advanced Topics Routing Policies RoutingTable RPCC RRPV RS RTI Rule Rule R31-DST-1 Rule WB-R31-5 runloop RunLoopInvariant RUNNING RunningState runOneInstruction RuntimeLogging S_Store SafeMemory SafeMemoryBoundary SafeMemoryIntegration SafeMemoryOffset Safety sample Sampling SanJose Saturating saveContext Saved PC Saved Processor Status SAVED_PC SAVED_PS saveExceptionAddress saveFaultVirtualAddress saveProcessorState saveSnapshot SC SC_Type Scalability Scalar ScalarFallback SCB SCBB scheduler SchedulerSupport Scheduling Scope Scoreboard Scratch ScratchRegion SCSI SDE SecondLevelDispatch SecurityBoundary SecurityModel seedEmulatrRandom Segment Selection SelectiveClear SelectorBits SelectorComputation selectVictim Semantic SemanticAuthority SemanticDomain SemanticExecution Semantics Separation Separation of concerns Seqlock sequence Sequencing serialization SerializationBarrier SerializationCondition SerializationEvent SerializationInteraction SerializationModel SerializationPoint SerializationPrimitive SerializationRequest SerializationScope SerializationType SerializedContext SERIALIZING SerializingState SerialLine ServiceHandler Set Prediction and Access Memory SetAssociative SetFpRegsFn SetIntRegsFn SetIprsFn setPC SetPredictionAndAccessMemory setReservation setTraceMask sext32 SFloat ShadowActivation shadowFpRegs shadowIntRegs ShadowRegister ShadowRegisterFile ShadowRegisters shadowRegsActive shard shard dimensioning shard index ShardBySize Sharded sharded cache benefits sharded cache requirements sharding Sharding & Lock-Free Design sharding concurrency sharding consistency sharding implementation sharding isolation sharding locality sharding mechanism sharding parallelism sharding scalability shards shareable interrupt, Device Interrupt Integration SharedGlobal SharedMechanism SharedMemory SharedPipeline SharedState Shift ShiftLeft ShiftOperation ShiftRight Shootdown Shutdown ShutdownRequest SideEffect SideEffectElimination SideEffectIsolation SideEffects Signal Signaling signBit signBitL signBitQ Signed SignedArithmetic signExtend signExtend16 signExtend21 signExtend32 signExtend8 SignExtension sigOffset SiliconSpeculation SIMD Simulation SingleEntry SingleExit SingleIssue SingleStep SingleStepFn Singleton SingletonPattern SIRR SISR Size SizeClass SizeClassId (enum) SLEEP sll Slot SlotFault SlotIndex SlotInvalidation SlotLevelStall slotSequence SlotState SlotValidity SMP SMP & Per-CPU Design SMP first-class design SMP guarantees SMP interrupt delivery, Architecture SMP Interrupt Handling SMP sharding SMPArchitecture SMP-aware subsystems SMP-capable SMP-capable design SMPCoordination SMPCorrectness SMPEvent SMPInteraction SMPInterrupts SMPManagement SMPManager SMPReservation SMPState SMPSynchronization SMPVisibility snapshot snapshotPath snapshotRegions SnapshotSlot Software Software Interrupt software interrupt IPL, Software Interrupts software interrupt request, Software Interrupts software interrupt routing, Software Interrupts software interrupt vector, Software Interrupts Software Interrupts SOFTWARE_IRQ SoftwareCompletion SoftwareConversion SoftwareInterrupt SoftwarePolicy SoftwareTLB SoftwareTrap Source SourceOfTruth SP Space Space Management Pages, PTE SPAlign SPAM SPAM manager shards SPAM sharding SPAMBucket SPAMEntry SPAMEpoch SPAMShardIPRManager SPAMShardManager SPAMShardManager AlphaCPU SPAMShardManager best practice SPAMShardManager code sample SPAMShardManager concrete type SPAMShardManager configuration SPAMShardManager constructor SPAMShardManager constructor injection SPAMShardManager cpuCount SPAMShardManager CPUStateIPRInterface SPAMShardManager CTOR SPAMShardManager dependent class SPAMShardManager direct pass SPAMShardManager DTB SPAMShardManager dynamic allocation SPAMShardManager example SPAMShardManager fast lookup SPAMShardManager global instance SPAMShardManager global manager SPAMShardManager idiom SPAMShardManager index SPAMShardManager initialization SPAMShardManager instantiation SPAMShardManager interface SPAMShardManager invalidation policy SPAMShardManager ITB SPAMShardManager lifetime SPAMShardManager manager vector SPAMShardManager member variable SPAMShardManager ownership SPAMShardManager per-CPU SPAMShardManager per-realm SPAMShardManager per-size-class SPAMShardManager per-system SPAMShardManager pointer SPAMShardManager pointer passing SPAMShardManager reference SPAMShardManager reference passing SPAMShardManager retrieval SPAMShardManager sharding SPAMShardManager shared_ptr SPAMShardManager SMP SPAMShardManager SMP support SPAMShardManager SMPManager SPAMShardManager storage SPAMShardManager system manager SPAMShardManager system-level storage SPAMShardManager template alias SPAMShardManager template parameters SPAMShardManager TLB manager SPAMShardManager traits SPAMShardManager traits specialization SPAMShardManager type alias SPAMShardManager unique_ptr SPAMShardManager usage SPAMShardManager victim policy SPAMShardManager wiring SPAMTag Span SparseMemoryBacking SPE Specification Specification vs implementation Speculation Speculation restraint SpeculationBlock SpeculationBoundary SpeculationDiscard SpeculationModel SpeculationRecovery Speculative SpeculativeDiscard SpeculativeExecution SpeculativeInstruction SpeculativePolicy SpeculativeSlot SpeculativeState Splitmix spurious interrupt detection, Debugging and Diagnostics SQRTS SQRTT SquareRoot Squash sra srl SRM SRM console firmware SRM firmware SrmBase SRM-D SrmDonePC SRMFirmware SrmInitialPC SrmLoaderConfig SrmMaxSteps SrmMirrorPA SrmRomDescriptor SrmRomLoader SrmRomLoadResult SrmSnapshot SrmSnapshotDir SrmSnapshotMemRegion SRRIP SRRIPPolicy SSE SSE2 SSE3 SSP SSSE3 StableMemory StackAlignment StackLimits StackPointer stack-pointer Stage STAGE_COUNT stage_DE stage_EX stage_IF stage_IS stage_MEM stage_WB StageArray StageClear StageCompletion stageDTB0PTE stageDTB1PTE stageDTBCommon StageExecution StageExecutionOrder StageIndex StageInvalidation stageITBPTE StageOrdering StageSequence StageValidity StaleData Stall StallCondition stalled StallGranularity StallModel stallPipeline StallReporting StallScope StallSource startElapsedTime StartOperation StartPA startPC StartupInitialization StartupSequence State StateAuthority StateCommit StateConsistency StateIsolation stateless policy StateMachine StateMaintenance StatePreservation StateRestore StateSnapshot StateTransition StateTransitions StateUpdate StateVisibility Static Re-Reference Interval Prediction StaticLocalInstance Statistics Status StatusBit StatusRegister STB StdStringLogging SteadyState Step STF STG STL STL_C STOLOAD stopCPU StopOperation Storage Store StoreCommit StoreConditional StoreConditionalFailure StoreData StoreInstruction StoreOperation StoreOrdering STOSTO STQ STQ_C STQ_U Strategy Strict priority ordering StrongBarrier StronglyNotTaken StronglyTaken Structure STS STT stub StubSpacing STW STx_C SUB Sub64 subBorrow SUBL SUBLV SUBL-V subOverflow subQ SUBQV SUBS Subset SubsettedInstruction Subsystem Subsystem responsibilities SubsystemAccess SubsystemOrchestration SUBT Subtraction success Summary superpage SuperpageEncoding Supervisor Stack Pointer SupervisorMode supplyFetchResult Sweep sweepDeadForASN swiLevel SWPCTX SWPPAL SymmetricMultiprocessing Synchronization SynchronizationIssue Synchronous SynchronousEvent SynchronousFault SynchronousLoad syncMemoryBarrier SyntheticStack Syscalls SYSPTBR system architecture System contracts System Control Block Base System execution System Interrupt System shape SystemArchitecture SystemAuthority SystemBusError SystemConfiguration SystemControlBlock SystemDataError SystemEvent SystemInitialization SystemIntegrity SystemManager SystemOperation SystemParityError systemPaused SystemReferenceGuide SystemReferenceManual SystemReset SystemService systemStarted systemStopped SystemTrap system-wide sharding system-wide TLB manager Table Tag TagKey TAGType Target TargetCPU TargetPC TBCHK TBI TBIA TBIAP TBIS TBISD TBISI TBMissBuffer TC-SNAP Technology Telemetry template instantiation template policy TemplatePolicyBase TemplatePolicyBase.h temporal locality TemporalIsolation TemporalModel TerminalControl Termination Testability testing TFloat Thread thread safety thread sharding ThreadContext ThreadingModel ThreadLocalStorage Thread-safe Interrupt ThreadSafety Throughput tick TickInvocation TickMethod TickOrder Time Timer TimerInterrupt timestamp Timing TimingModel TimothyPeer TLB TLB & Coherency TLB (Translation Lookaside Buffer) TLB cache TLB interface wiring TLB isolation TLB manager instantiation TLB manager pattern TLB parallelism TLB sharding TLB shootdown IPI, IPI Integration TLB shootdown, IPI Integration TLBControl TLBEntry tlb-eviction TLBFill TLB-fill TLBFlush TLBIndexing tlbInsert TLBInvalidate TLB-invalidate TLBInvalidation TLBIsolation tlbLookup TLBManipulation TLBMiss TLBReplacementPolicy TLBShootdown TLB-shootdown TLBTag tlbTBIS TLBTranslation TLS toDtbPteRead toItbPteRead Top-level architecture TotalSize Tournament Trace TRACE_ALL TRACE_EVENT TRACE_FP TRACE_INSTR TRACE_INTEGER TRACE_MEMORY TRACE_NONE TRACE_PAL TRACE_PIPELINE TRACE_TLB TraceCore TraceLogging TraceMask TraceReplay Tracing Tracking Training Traits Traits template Traits type alias Traits-based manager TransitionVisibility Translation Translation Buffer TranslationBuffer TranslationBypass TranslationControl TranslationEngine TranslationFault TranslationLookasideBuffer TranslationRealm TranslationResult Trap TrapAmbiguity TRAPB TRAPB barrier TrapBarrier TrapBit TrapClearing trapCode TrapCode_Class TrapCompletion TrapContext TrapDeferral TrapDelivery TrapDispatch TrapEnable TrapEntry TrapEvent TrapHandler TrapHandling TrapLifecycle TrapMask TrapOrdering Trapping TrappingVariantSupport TrapRecording TrapReleaseCondition TrapResolution Traps TrapSemantics TrapSerialization TrapSummary Trigger Tru64 Tru64 UNIX Tru64 UNIX compatibility Tru64UNIX Tsunami TSV twoComplement TwoPhaseModel type alias TypeConversion typedef TypeDefinition types types_core_h UMULH Unalign Unaligned UNALIGNED_ UnalignedAccess Unconditional Underflow Understood — here is a **refined, normalized vertical noun-only k-keyword list** for Sections 2.7.1–2.7.2, cleaned for architectural consistency and keyword indexing (PascalCase, noun-form, no verbs, no function-style tokens): Uniform Unique Value unit Unlikely UnmappedRegion Unordered UnprivilegedCallPal UnprivilegedFunction UnprivilegedMode UnprivilegedRange UNQ Unreachable Unsigned Update updateExceptionIPRs updateExceptionSummary updateMemoryManagementStatus updatePrediction URTI Usage Usage Guide USE_EMBEDDED_SRM useEmbedded User Stack Pointer UserMode UserReadEnable user-stack UserWriteEnable using USP Utf8Logging UTILITY v6_2 v7_2 VA VA (Virtual Address) VA32 VA-32 VA48 VA-48 VABits VA-form VAFormat valid valid flag validation ValidBit Validity ValidityFlag ValuePropagation Variant vaTop VAType VAX VAXCompatibility Vector VectorBase VectorCalculation VectorClassification VectorDispatch VectorEntry VectorEnumeration Vectorization Vectorized VectorMapping VectorOffset VectorRange VectorResolution VectorStride VectorTable VendorBehavior Verifiability Verification Version_0_9 victim policy selection victim selection policy VictimPolicy Violation Virtual Virtual Interrupt Virtual Page Table Base VirtualAddress VirtualAddressSpace VirtualMemory VirtualPage VirtualPageNumber VirtualPageTableBase Visibility VisibilityGuarantee VMM VMS Interrupt Model VPN VPNType VPTB VT100 Vtable WaitingState WallClock Warmup WARN_LOG Warning WB WBStage WeaklyNotTaken WeaklyTaken WeakOrdering WH64 WH64EN WHAMI Width Wildcard Wildfire Windows WindowsNT WMB WMB barrier Word Work Workload WR_PS WritableRAM Write WRITE_UNQ WriteAPI Writeback Writeback commit point WritebackStage WriteBarrier WriteBuffer WriteBufferDrain writeBufferDrained WriteBufferEntry WriteBufferManager WriteCompletion writeDecLine writeElapsedToMachineLine WriteFault writeFpReg writeIntReg writeMachineLine WriteMemoryBarrier WriteOnlyBarrier WritePermission WritePhysicalFn WriteSemantics WRVPTPTR x86_64 XOR YoungerSlot YoungestInstruction ZAP ZAPNOT Zero zeroExtend zeroExtend16 zeroExtend32 zeroExtend8